CEO McWilliams bills the technology as "the lowest cost solution out there" to compete with 3-D transistors and SOI. "We think the cost of adopting this is negligible for fabs, and the improved voltage variations it brings also will help them improve their overall yields," he said.
The transistors require no new tools, mask layers or materials, but they do require some new process steps. McWilliams believes the transistors can be used at any process node from today mainstream 65nm process to a future 14nm generation.
If it gains adoption with fabs, SuVolta will turn its attention to selling circuit libraries that could leverage the underlying transistors to cut power dissipation in half yet again. The startup has already taped out devices using such circuits.
Thompson knew the potential significance of what he discovered. He helped Intel develop its 45nm high-K metal gate technology and critiqued work on 3-D transistors that Intel recently announced for use in its 22nm node.
Two of Thompson's colleagues at Intel actively worked on Intel's 22nm tri-gate transistor program and now work at SuVolta---Lucien Shifren and Pushkar Ranade.
"It’s a very good solution for high performance, high power processors, but if you are trying to serve an industry and reuse legacy IP it would be difficult to adopt," Thompson said of Intel's tri-gate transistors.
SuVolta still faces financial challenges. The company took on $30 million in VC financing before McWilliams and Thompson came on board in 2009. A year ago it closed a Series D round for another $22 million.
McWilliams said SuVolta will need at least one more funding round before it can be self-sustaining. It hopes to close that round later this year or early in 2012.
So far, the startup has just one licensee, Fujitsu. However, it claims it is in negotiations with other potential licensees. It is asking for royalties either on a per-product or per-wafer basis.
The company currently has 40 employees, and expects to hire as many as another 60 "over the next few years," said McWilliams.
One potential weak spot for the company is that it has yet to be awarded any patents on its work. It has filed about 20 patents to date in the U.S. where approvals take an average of three years. It also has filed a few patents in Europe where the approval process tends to be quicker.
The patent office delays haven't stopped SuVolta from disclosing some details of its technology to potential partners, some of whom supplied quotes of support for its announcement.
"SuVolta’s low-power platform could have a dramatic impact on the industry," said Pieter Vorenkamp, senior vice president of operations engineering at Broadcom.
"The substantial device matching improvement of core and IO devices, enhanced body
effect and perceived 'simple' integration with a digital CMOS manufacturing flow are momentous and could have a dramatic impact on reducing power and cost of
highly-integrated SoCs," said Vorenkamp.
"SuVolta has developed an innovative way to significantly reduce CMOS transistor active and leakage power," said T.J. Rodgers, founder and CEO of Cypress Semiconductor.
"By tightening threshold voltage variability while maintaining performance at lower supply voltage, SuVolta’s platform extends the useful life of bulk planar CMOS processes and the products they enable and negates the need for costly, complex technologies like EUV lithography, FD-SOI or FinFETs," Rogers said. "Furthermore, the technology enables companies to preserve and extend the legacy IP blocks they have spent years developing,” he added.
SuVolta "enables a mature 65nm process to deliver performance per watt characteristics comparable to advanced 32nm processes," said Nathan Brookwood, principal of market watcher Insight 64 (Saratoga, Calif.). "While some argue that the industry must move to 3-D transistor structures now, SuVolta shows that rumors of the death of the planar transistor have been greatly exaggerated,” he said.
Industry veteran Ron Wilson of EDN Magazine was more skeptical in his analysis, based on a review of a Powerpoint presentation from the company.
"On the surface, it appears that this is a stop-gap that will only be of interest to marginal foundries trying to prolong the life of fabs they can’t afford to upgrade," Wilson said.
He also noted chip designers would have to weigh the promise of a 50 percent power reduction using new circuit designs with the time and cost it would take to verify a new chip design.
This would be a great breakthrough for the semiconductor industry, both for low power mobile type of applications and for large scale chip designs (lower heat, lower power, better performance). I really want to cheer for the start-up that roars!
I agree they have a chance Nic but looking at the patent application is not entirely clear how one controls exactly position of the dopants which is the key to their low power claims...I am actually amazed that a few people can still get together and challenge well established transistor manufacturing concepts that billion dollar corporation work on with thousands of people on board...cheering for a small guy then, go SuVolta go! Kris
Fujitsu collaboration with SuVolta on this development making the technology available at 65nm process node is an assured step in the commercialization of the technology. And the company's executive slate has impressive players. So overall, I would give the technology a chance to prove itself but I would caution inflated claims to "halfing" power of ICs. What is achievable at the device level may not necessarily translate linearly at the integrated circuit level for acceptable volume production yields.
@iniewski: BTW, a sentence or two of your views here may encourage others to come to you for more in-depth consulting and analysis. Please invite Ashok to chime in...and a question, what kind of process was the JFET based on originally?
Kris, the slides Ashok presented at the conference you mentioned are on JFET stuff. Since then, SuVolta abandoned that approach. The news released today is on bulk CMOS based PowerShrink technology.
Please visit the company website to learn more about this groundbreaking technology...Sang-Soo
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.