SAN JOSE, Calif. – SuVolta comes out of stealth mode Monday (June 6) with a transistor design that promises to cut power dissipation in half for fabs that adopt it. The startup also is working on circuit designs that could further slash power for chip designers who use fabs with SuVolta's transistors.
At a time of diminished venture funding for semiconductor startups, SuVolta stands out for the caliber of its experts and backers. The company employs three tech executives who had some involvement in Intel's pioneering 45 and 22nm process technologies, and it has three of Silicon Valley's veteran VCs on its board—Forrest Baskett, Bill Joy and Andy Rappaport.
But SuVolta's challenges are as daunting as its pedigree. The company must pioneer a business model initially focused on selling intellectual property to fabs, a new kind of sale to customers more accustomed to buying capital equipment.
Success could open doors for other startups in the rarified world of silicon process technology. It also would win SuVolta the opportunity to try to convince circuit designers they should adopt a whole new set of libraries to gain additional power reductions.
The first step may be the hardest. To establish itself, SuVolta must prove it has found a new and worthwhile alternative to technologies such as 3-D transistors and fully depleted silicon-on-insulator processes, techniques born of some of the smartest minds in semiconductors.
So far, SuVolta has made modest but noteworthy progress on that goal. The company built in a Fujitsu fab a 65nm SRAM device that is acting as a proof of concept. It also reports promising early test results at 28nm.
Fujitsu is enamored enough of progress to date it claims it will use the SuVolta technology in all its products and will ship the first chips using it sometime late next year. SuVolta also has disclosed the technology, at least in part, to companies such as Broadcom and Cypress who provided glowing comments for its public debut.
SuVolta is already on its second go-around as a startup. Backers invited current chief executive Bruce McWilliams and CTO Scott Thompson to conduct an analysis of the company in 2009, three years after it was founded by other execs under the name DSM. Three months into their analysis, Thompson, a former Intel process tech expert, had a eureka moment.
Thompson realized the startup's design for a junction field effect transistor (JFET) could be applied to bulk CMOS to precisely control voltage levels without reducing signaling speed. That implied the potential for reading and writing data at much lower voltages than previously imagined.
After such a big Aha! moment, "you recheck the derivations to be sure you are right because you are nervous," said Thompson. "I felt cautious for the next month because I wanted to make sure we could build [planar, bulk CMOS]," he said.
"After the first month, I was confident it was going to work, but it took us a year to build SRAMs, and the more conservative people at the company were convinced only when the SRAM came back from the fab," Thompson added.
That SRAM—a 220 million gate device—has hit acceptable yields in low volume production with all its modules working. It can read and write data at power levels as small as 0.42 of a volt. Today's SRAMs require at least 0.8 volts.
So far, the startup's data on its approach in 28nm involves building simple structures of a few hundred gates. Those designs have not been proven yet to hit acceptable yields. SuVolta has not disclosed where the 28nm work is being done, but said it "has partnerships" with two foundries.
Kris, the slides Ashok presented at the conference you mentioned are on JFET stuff. Since then, SuVolta abandoned that approach. The news released today is on bulk CMOS based PowerShrink technology.
Please visit the company website to learn more about this groundbreaking technology...Sang-Soo
Rick, yes, I am totally independent of Su Volta...they make very impressive claims, but we all know how tough it is to come up with something really innovative after 50+ years of silicon developments...I have not analyzed the claims, would be happy to, my PhD was in MOSFET modeling afterall, but someone would have to pay me for that service ;-)...alternatively we can ask Ashok Kapoor (author of the talk in Whistler) to comment...Kris
@iniewski: BTW, a sentence or two of your views here may encourage others to come to you for more in-depth consulting and analysis. Please invite Ashok to chime in...and a question, what kind of process was the JFET based on originally?
Fujitsu collaboration with SuVolta on this development making the technology available at 65nm process node is an assured step in the commercialization of the technology. And the company's executive slate has impressive players. So overall, I would give the technology a chance to prove itself but I would caution inflated claims to "halfing" power of ICs. What is achievable at the device level may not necessarily translate linearly at the integrated circuit level for acceptable volume production yields.
I agree they have a chance Nic but looking at the patent application is not entirely clear how one controls exactly position of the dopants which is the key to their low power claims...I am actually amazed that a few people can still get together and challenge well established transistor manufacturing concepts that billion dollar corporation work on with thousands of people on board...cheering for a small guy then, go SuVolta go! Kris
This would be a great breakthrough for the semiconductor industry, both for low power mobile type of applications and for large scale chip designs (lower heat, lower power, better performance). I really want to cheer for the start-up that roars!