SAN JOSE, Calif. – Six OEMs will show systems running a prototype version of Intel's Many Integrated Core architecture (MIC) at this week's International Supercomputer Conference. Intel will also report progress programming the highly parallel coprocessor eared for high performance computing clusters.
Colfax, Dell, Hewlett-Packard, IBM, SGI and Supermicro all will show systems using the prototype MIC chips. At least one research organization will share its experiences porting applications to the architecture using about 32 cores on a MIC chip.
The current chip, called Knights Ferry, is not intended as a commercial product, in part because it does not support double precision floating point operations. A future version, called Knights Corner and made in Intel's 22nm tri-gate process will support double precision, but Intel is not yet announcing when it will ship.
In addition, MIC currently relies on a mix of Intel proprietary programming tools and standards such as OpenMP. The Knights Corner product will also support the OpenCL API standard backed by archrival Advanced Micro Devices for its competing chips.
MIC represents Intel's implementation of a kind of many core, graphics-based processor targeting use as a general-purpose accelerator for highly parallel applications. It will compete with AMD's Radeon chips using OpenCL and Nvidia's graphics chips using its proprietary CUDA environment.
So far, Nvidia has a lead in this space which supports relatively few users buying chips at generally high prices and profit margins. For example, of 19 of the Top 500 supercomputers in the latest rankings that use graphics accelerators, 12 of them use Nvidia chips.
Intel claims it will have an advantage in this space because its MIC chips will use x86 cores. Users will be able to program them more easily than competing GPUs because they will use existing x86 server programming tools, Intel claims.
A technology executive from SGI said the majority of its users interested general-purpose graphics accelerators are interested in the relative ease of programming promised by the MIC architecture. However, he said the company is sees a range of performance characteristics across different applications with the current MIC chips.
The MIC "performance ranges dramatically based on applications from orders of magnitude improvements to incremental improvements" using the current chips that support only single-precision floating point operations, said Eng Lim Goh, chief technology officer at SGI.
"You end up with two kinds of customers, one highly satisfied with [AMD and Nvidia graphics] accelerators because despite the tedious porting process, their results are very good," Goh said.
"Others feel their time spent on porting [their apps to AMD and Nvidia chips] doesn’t justify the performance and there is a huge part of this second group for whom MIC is useful—and ultimately some of the first group may want MIC, too," he said.
Goh showed one application that could tap into the many-core MIC chip using just a single line of additional Open MP code.
Goh and an Intel representative said the MIC architecture also promises to help supercomputer makers deliver exascale-class systems by about 2018, a target for which some are aiming. Today's fastest system is approaching 10 petaflops without the use of accelerators.
Intel has said its Knights Corner product will pack more than 50 x86 cores. Intel's road map for MIC promises even higher core counts in the future, said Goh.
An Intel executive will say at the supercomputing event that the company plans to use MIC to help deliver some of the first exascale-class systems.