SAN FRANCISCO—Researchers from the Massachusetts Institute of Technology say they have developed a technique for pushing the resolution of high-speed e-beam lithography to write patterns for chips as small as 9-nanometers across, much smaller than previously thought possible, according to a posting on MIT's website.
According to MIT, the smallest feature sizes that e-beam lithography tools have previously been shown to resolve were 25-nm across. The findings, to be published in a forthcoming issue of Microelectronic Engineering, could place e-beam lithography back into the discussion of future lithography technologies for semiconductor manufacturing.
Extreme ultraviolet lithography (EUV) has for years been considered the front runner to succeed current optical lithography. The introduction of EUV into volume manufacturing has been pushed out several times, and is currently expected to be introduced into manufacturing at the 22-nm half-pitch node in 2012 and 2013 at leading IC manufacturers.
However, EUV continues to be dogged by issues including creating a sufficient power source and the lack of an EUV pellicle to protect the photomask from contamination.
Researchers have long pursued development of e-beam lithography, which is thought to have inherent resolution advantages over other technologies. Direct-write e-beam lithography is also an attractive technology because it eliminates a very costly item in modern chip making—the photomask.
However, the technology has been dogged by throughput issues—the write time of an e-beam is painfully slow compared to other technologies. E-beam tools are used in photomask writing, but many believe the technology will never be fast enough for high-volume semiconductor lithography. Several companies and research institutes are currently developing e-beam tools for direct write lithography and other niche applications.
According to MIT, in e-beam lithography, a beam of electrons scans across the surface of the chip's photoresist, row by row, as opposed to current photolithography, where light shines through a maks, striking the whole surface of the chip at once.
The MIT researchers— Vitor Manfrinato, an RLE graduate student and first author on the new paper, Karl Berggren, associate professor of electrical engineering and computer science, professor of electrical engineering Henry Smith and several graduate students—said they used two tricks to improve the resolution of high-speed e-beam lithography. The first was to use a thinner resist layer, to minimize electron scattering. The second was to use a solution containing ordinary table salt to “develop” the resist, hardening the regions that received slightly more electrons but not those that received slightly less.
Pieter Kruit, a professor of physics at the Delft University of Technology in the Netherlands and co-founder of direct-write lithography system developer Mapper NV, was quoted on the MIT website saying he doubts manufacturers will use exactly the resist that the MIT researchers did in their experiments. Although the researchers’ goal was to find a resist that would respond to small doses of electrons, the one that they settled on is actually “a little bit too sensitive,” according to Kruit.
“But that is a matter of modifying the resist slightly, and that’s what resist companies do all the time,” Kruit said.
I've watched e-beam and x-ray/EUV (let us keep reminding ourselves that despite the name change, e-beam's birth name was SXPL: soft x-ray projection lithography, and it remains SOFT X-RAY) developments for ~40 years. X-ray has proven to be too difficult, and remains so in its EUV disguise. All e-beam developers have made the classic mistake of pursuing silicon first (where there is no real suction) and mask making in desperation (because direct write on silicon has several key non-ebeam issues) too late. E-beam developers would be wise to pursue mask making first (make masks faster, more precise and cheaper) and silicon as an adjunct.
As a followup, I have seen (published) evidence of E-BEAM written structures as small as 100Ang (10nm) in thick resist as far back as 1990. Check out the abstracts of the EIPBN conferences at http://eipbn.org.
Even with reduction lithography, the CD of the mask patterns for 9mn lithography will need to be 90nm (for 10X reduction systems) or 45nm (for 5x reduction systems), very unlikely to be achievable, and very costly! At 1X (for EUV or X-RAY systems), it will be prohibitive. It's becoming increasing clearer that E-BEAM is the NGL (Next Generation Lithography). Considering the cost differential of a good E-BEAM system (~$5M) vs. a proposed EUV system ($50M to $100M), why not simply commit to buying multiple E-BEAM systems to make up the offset in volume? The savings in masks alone will be substantial, and the advantage in system redundancy alone would be enormous!!! Add to that, the technology exists right now, and has (in one form or another) for over 30 years!
Even with reduction lithography, the CD of the mask patterns for 9mn litho will need to be 90nm (for 10X reduction systems) or 45nm (for 5x reduction systems), very unlikely! It's becoming increasing clearer that E-BEAM is the NGL (Next Generation Lithography). Considering the cost differential of a good E-BEAM system (~$5M) vs. a proposed EUV system ($50M to $100M), why not simply commit to buying multiple E-BEAM systems to make up the offset in volume? The savings in masks alone will be substantial, and the advantage in system redundancy alone would be enormous!!!
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.