NEW YORK—Test and measurement vendor Tektronix Inc. Tuesday (July 5) announced the acquisition of ASIC/FPGA prototyping debug software provider Veridae Systems Inc. Terms of the acquisition were not disclosed.
Veridae (Vancouver, Canada) was founded in 2009 to commercialize research from the University of British Columbia. The firm sells three tools for ASIC/FPGA prototyping debug, ASIC post silicon validation and FPGA-based system product validation into semiconductor and system product companies.
Veridae's products—including the recently launched Certus FPGA prototyping suite—offer a systematic "design for validation" approach, according to the company.
"Veridae is solving an ever increasing challenge faced by our customers—debug and validation of their complex systems," said, Amir Aghdaei, president of Tektronix, in a statement.
Tektronix (Beaverton, Ore.) said it would establish Veridae as an embedded capture business unit, remaining in Vancouver.
"We’re excited to be part of the Tektronix team and to establish a business unit for the company in Vancouver," said Jim Derbyshire, Veridae's CEO and a mentor in residence at Simon Fraser University. "This allows us to maintain our close ties to the local research community, which were instrumental in the founding of Veridae."
Veridae launched Certus, a multi-FPGA prototyping debug suite that enables a single view of complex ASIC designs, last month.
"Certus was designed by IC designers aiming to solve the challenges associated with prototyping, debug and verification of today’s faster, more integrated FPGA-based systems," said Derbyshire.
The Certus suite for FPGA prototyping provides a synchronized view of the entire system, including serial I/O, busses, software code and FPGA hardware. Certus does not require custom connectors or I/O resources and can be deployed on all existing platforms.
Certus is based on Veridae’s proven set of software tools that includes the Implementor, which helps to design and implement minimized on-chip signal capture probes; the Analyzer, which manages the captured data; and the Investigator, which relates the information back to the design, interpolates the data and displays a larger signal set.
The combination of these tools allows designers to have a single synchronized view for faster FPGA-based system validation and debug without endless re-synthesis and place and route.