SAN JOSE, Calif. – The RapidIO Trade Association announced a roadmap to take its interconnect to serial lane speeds of 10 and 25 Gbits/second.
A specification for a Serial RapidIO 10xN standard should be complete by the end of the year. It will support up to 16 10 Gbit/s lanes using the physical layer defined by the IEEE 10GBase-KR standard. The group plans a follow on based on a 25 Gbit/s IEEE standard now in the works.
The 10xN effort marks a third generation for RapidIO. Its Gen2 spec defines links that run at 5 and 6.25 Gbits/s.
The 10xN spec will carry over the existing transport and protocol parts of the Gen2 spec, including support for virtualization. No major new features beyond the data rate boost are expected in the new spec.
RapidIO is widely used on DSPs, especially in applications such as LTE and WiMax base stations and military VME cards, said Tom Cox, executive director of the RapidIO Trade Association. The link appears in chips from Freescale, LSI, Mindspeed, NetLogic and Texas Instruments, he said.
The 10xN standard will define a short-reach specification for links spanning 20 cm and two connectors. A long-reach specification will support distances up to a meter and two connectors. With 10xN, the group plans to move away from its 8b10b encoding scheme to a more efficient alternative yet to be named.
RapidIO is seen as an embedded-friendly alternative to PCI Express and Ethernet, two interconnects much more widely used in board-level designs in computing and communications.