SAN FRANCISCO—Texas Instruments Inc. said Wednesday it has shipped more than 30 million power management devices featuring its PowerStack 3-D packaging technology, which the company says offers performance, thermal, power consumption and board space advantages compared with conventional packaging technologies.
Matt Romig, analog packaging product manager at TI, said the PowerStack technology is the first 3-D packaging technology to stack high-side vertical mosfets. PowerStack combines both high-side and low-side mosfets held in place by copper clips and uses a ground potential exposed pad to provide thermal optimization, Romig said.
TI has been shipping power management devices with PowerStack for about a year, Romig said. So far, most of the adoption has been in applications that require very high performance such as telecomm equipment and servers. "This isn't something you are going to see in a cellphone or a tablet," Romig said.
PowerStack's combination of stacking and clipping techniques provide significant benefits over traditional side-by-side discrete mosfets, according to Texas Instruments.
According to TI, PowerStack uses TI's NexFET power mosfets, stacked on a grounded lead frame, using two copper clips to connect the input and output voltage pins. This combination of stacking and clip bonding results in a more integrated quad flat no-lead (QFN) package, according to the company.
TI says the PowerStack approach reduces the size of a package by as much as 50 percent compared to packages that position mosfets side-by-side. The company says that PowerStack improves efficiency, reduces power consumption by nearly 20 percent, and provides an optimal thermal configuration that cuts temperatures by more than 30 percent.
"PowerStack is the first packaging technology I’ve seen like this in the power arena," said Jan Vardaman, president and founder of TechSearch International. "Momentum for 3-D packaging solutions is growing, and this technology is well suited to address a number of current and next generation design challenges."
Romig said that being a "packaging guy," it was exciting for him to be involved in a product where the packaging is the key selling point. "This is really a case where the packaging tech and packing implementation really is a big differentiator," Romig said.
PowerStack is in volume production today at TI’s Clark facility in the Philippines, the company said.
I kind of agree with Dr. Divakar. This is one of the simpler more established examples of 3D packaging, and doesn't touch on the issues that for example, TSV-based systems might face, such as accumulating thermals, keep-out zones and parasitics.
3D package is a good idea, if the cost of manufacturing won't up much and yield can still maintain good. Power device surely is a good idea, especially the way the MOSFET is placed can't be no more shorter than this! Hope to see more companies jump into this area and produce smaller yet powerful products.
I think the point here is not whether or not the technology is new, but how well it is implemented, manufactured, and shipped in volume. And yes, we should expect to see many more devices in the future using this technology in more complex ways.
@Dylan: I hate to rain on TI's parade but there is not much new in their "vertical" technology. Back in 2003, I worked on this idea (along with a former colleague at Power One) and extended it to integrate the MOSFET driver in the same package using Carsem's 38Lead MLP Quad Package (8x4mm). The innovation also used Cu-clips to bond with the source digit-like source pads.
The source-to-drain stacking between high side and low side MOSFETs can be done with yesterday's technology, not needing any TSV's!
I understand IR and other power electronics players were also working on similar concepts.
This is very good news. With advent of this 3D packaging, TI can introduce many novel features in their product and make SoC very effective. We will see many more product with more complex 3D packaging technology.
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