Even though the final cognitive computers will have billions of neurons, they will only consume power when a neuron fires, which happens at the incredibly slow clock speed of 10 Hz. As a result, an entire brain-sized cognitive computer could fit into a shoebox and consume less than a thousand watts.
IBM showed two working prototype chips, both completely digital, which it hopes will serve as the cores of future cognitive computers where thousands will be integrated on multi-core chips.
"A key intellectual step forward was that our chips are all digital, allowing us to simulate on a supercomputer and then implant the results on a silicon chip, resulting in predictable, deterministic behavior," said Modha.
Its two prototypes each use a few million transistors to implement a single core housing just 256 neurons and consuming less than four square millimeters in area using IBM's 45-nanometer silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The only difference between the two test cores was in their use of the interconnecting crossbar array, either as 256k pre-programmable synapses, or as 64k learning synapses. The chips were fabricated at IBM's facility in Fishkill, N.Y., and are currently being testing at the T.J. Watson Research Center in Yorktown Heights, N.Y. and at IBM Research in San Jose, Calif.
In operation, IBM's chips learn from experience, after several learning parameters are set. For instance, one parameter is the threshold level at which neurons fire after integrating over their multiple inputs, allowing faster but cruder operation when set low, or slower but more refined operation when set high. Then as the neurons fire, the learning synapses adapt by changing their weights as they are used. IBM implements the (Donald) Hebb rule, whereby the more a synaptic connection from one neuron to another is used, the more conductive it becomes by virtue of lowering its synaptic weight. Seldom used pathways, on the other hand, inherit higher weights that virtually prune them from the neural network.
IBM envisions its cognitive computers solving a wide variety of applications in navigation, machine vision, pattern recognition, associative memory and classification. So far it has taught one to recognize a cursive letter "7" regardless of in whose handwriting. The other has learned to play (and win against humans) at the game "Pong."
You seem to be confused regarding the difference between programming a computer to beat people at Pong (which obviously happened when the Pong console came out) and having a computer learn to do the same thing. That's fine; being confused is fine. Matched with your arrogance, however, and your confusion becomes tiresome.
Say thanks a lot for your time and effort to have put these things together on this blog. Mary and I very much loved your ideas through the articles on certain things.
I have just been asked to explain the final sentence in my posting above, there was a typo. It should have read: "However, that path tends to lead to the conclusion that CBRAM might offer a superior solution." I meant the Conducting Bridge RAM, that offers, by electrochemical action the precision to add and remove individual layers of atoms. Without that is the need for melting, high temperatures and high current densities associated with "reset" in conventional PCM. Apologies.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.