Oracle is continuing its aggressive support of eight threads per core, started under the former Sun Microsystems. "We think we still lead in threads per chip, and we will continue to do so," said Robert Golla, a senior hardware architect at Oracle.
The new S3 core will be the basis for future Oracle processors. It sports extensive new branch prediction and pre-fetch features, a new dynamic threading approach for mixed workloads and a 16-stage integer pipeline running at more than 3 GHz. The core adds a handful of new instructions to boost performance on cryptography and some Oracle-specific apps.
Except for a new crossbar and cache design, the 40nm TSMC chip uses similar blocks as the prior T3 chip. The T4 has been running in lab all year but has not yet been released in systems.
Finally, Cisco Systems described Sereno, a 40 Gbit/s Ethernet ASIC it will use in its next-generation servers. The chip includes a mix of virtualization and networking features not found in merchant chips, Cisco engineers said.
Popular systems software such as Microsoft Windows Server and VMWare's ESX do not support the so-called SR-IOV virtualization defined by the PCI Special Interest Group. So Cisco designers created their own I/O virtualization technology for its chip, letting it act as up to 256 Ethernet virtual interfaces to the system, each with its own VLANs, multicast, filters and other capabilities.
The chip includes a MIPS R24K processor to handle network management jobs, including tracking up to 16 million network flows, offloading work from the server host CPU. The chip also groups its interrupts so as not to generate "interrupt storms" that swamp the host processor.
The 65nm chip was made at Texas Instruments, is running in the lab and going through system-level testing to ship with future Cisco servers.