Chiang suggested immersion lithography would be too expensive at 14 nm, exceeding traditional guidelines of half the capital equipment costs for a node. Despite the enormous costs of EUV and e-beam machines, estimated at as much as $120 million, they are still cheaper than immersion given the double patterning problems.
E-beam and EUV systems cost roughly the same. But E-beam systems currently under test do not require masks so could slightly cheaper to use than EUV, Chiang said.
EUV has "the broadest support and is the most likely route" forward, said Luc Van den hove, chief executive of the Imec research consortium based outside Brussels. "But this year and next we have to demo the production worthiness of this technology," Van den hove said in a separate talk.
Imec has been running wafers through an ASML 3100 pre-production system for three months "and we've seen improvement in throughput, but progress has been too slow and we have to further accelerate it," he said.
The power of the EUV source light is still too low, despite defining two approaches to creating the light source. "Progress has not been sufficient, and this is one of the highest priorities," said Van den hove who once ran Imec's lithography program.
As if the capital equipment problems were not enough, TSMC expects it will need to transition to a new transistor design at 14 nm, likely a FinFET. Intel announced plans to use such a 3-D transistor design starting at 20 nm.
Both TSMC and GlobalFoundries believe planar transistors can be used down to 20 nm. But they both expect to make the switch to 3-D structures such as FinFETs or fully depleted SOI at 14 nm.
Van den hove said FinFETs "are probably the most likely way. Beyond that we believe another technology breakthrough will be needed likely using super-high mobility materials such as germanium p-channel and III-IV materials for n-channels for 10 nm nodes," he added.
The good news is unexpected innovations have powered the industry past roadblocks in previous generations, despite as many as ten past predictions that Moore's law would end, said Chiang of TSMC. Based on feasibility demonstrations, he projected currently defined technologies could take CMOS scaling to geometries as fine as 7 nm.
E-beam lithography could have the lowest costs, TSMC said.