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TSMC says equipment vendors late for 14-nm

9/7/2011 10:08 AM EDT
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resistion
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re: TSMC says equipment vendors late for 14-nm
resistion   9/7/2011 12:30:50 PM
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I think tsmc will be ok with DP if the volume per mask goes up a lot. This will happen if they gain market share against GF and Samsung. Otherwise, if market share loss is imminent, maskless would give them more agility.

resistion
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re: TSMC says equipment vendors late for 14-nm
resistion   9/7/2011 1:58:00 PM
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I should say market share meaning more customers giving 100% business to tsmc.

rfab
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re: TSMC says equipment vendors late for 14-nm
rfab   9/8/2011 4:04:21 AM
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1 think you"re tsmc"s pr

resistion
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re: TSMC says equipment vendors late for 14-nm
resistion   9/8/2011 8:39:02 AM
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This article was about tsmc, so I used tsmc as subject. I think GF is also investigating maskless (same reasons).

Or_Bach
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re: TSMC says equipment vendors late for 14-nm
Or_Bach   9/7/2011 10:20:53 PM
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More volume is not always make it better, some times it just means that you are going to loose more. Cost of next generation device could be less attractive if you account the true cost of capital -throughput - and yield. As the issues with the classic 0.7x scaling are mounting up it seems that the industry should make serious effort to explore the monolith 3D IC alternative. In fact I have no doubts that future progress needs to incorporate scale up if only to extend the useful life of the accelerating costs associated with next generation lithography.

resistion
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re: TSMC says equipment vendors late for 14-nm
resistion   9/8/2011 12:52:30 AM
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I agree the NGL is still not cost effective enough. But how does double patterning compare with stacking two wafers? It seems you still consume twice as much silicon area with stacking.

Or_Bach
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re: TSMC says equipment vendors late for 14-nm
Or_Bach   9/8/2011 3:41:41 AM
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Yes it appears so but it is not so. If we can stack two layers with rich vertical connectivity (monolithic 3D)you reduce by ~50% your average gate length which allow the average gate size (W/L) to be about 50% smaller which result in 50% reduction of active silicon area (Yes those repeaters and drive do consume area). Please feel free to use the IntSim v2.0 an open-source simulator available at http://www.monolithic3d.com/simulators.html to evaluate alternatives of device implementations and the implication on die size power and performance. And you get additional saving on equipment amortization cost, mature line yield and far lower masks cost.

resistion
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re: TSMC says equipment vendors late for 14-nm
resistion   9/8/2011 8:32:39 AM
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Ok, just asking, not judging. Counting process steps is a serious exercise. I will take a look at your simulators, thanks.

resistion
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re: TSMC says equipment vendors late for 14-nm
resistion   9/8/2011 8:52:47 AM
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So I have 2 GB DRAM by stacking 1GB on another one. But I still patterned a 1GB die twice.

RobDinsmore
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re: TSMC says equipment vendors late for 14-nm
RobDinsmore   9/8/2011 4:20:53 PM
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I don't understand why foundries/ logic companies keep talking about 450mm for 2015. I mean yeah, I get it, but it is pure fantasy at this point because nobody in the capital equipment industry has jumped in to support this yet and it will take a few years to get to the point where fabs can start developing their full flows and then the usual 2 until that flow is ready to ramp. I work in the industry and every time a colleague asks management about 450mm we get the same story they are telling the press. Namely that 450mm needs investment from customers or some yet to be decided collaboration to make it cost effective for equipment vendors.

docdivakar
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re: TSMC says equipment vendors late for 14-nm
docdivakar   9/8/2011 5:57:11 PM
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@RobDinsmore: agree with some points you make above. The industry is still struggling with handling thinned wafers (like 3um, as in what is needed for 3D chip stacking) at 300mm. Handling thin wafers at 450mm will be exponentially harder. Secondly, there aren't many companies left in the test space to provide wafer probing gear (probe cards, test interfaces, etc) so the cost of NRE will be quite high. I think 450mm for 2015 is too optimistic unless the market needs change drastically by then. Dr. MP Divakar

docdivakar
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re: TSMC says equipment vendors late for 14-nm
docdivakar   9/8/2011 5:59:11 PM
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OOPS, I meant 30um above, not 3um!

krisi
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re: TSMC says equipment vendors late for 14-nm
krisi   9/8/2011 6:14:57 PM
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There is no way we will see 14nm chips in 2015. I am willing to make financial bets;-). Pls email kris.iniewski@gmail.com

any1
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re: TSMC says equipment vendors late for 14-nm
any1   9/8/2011 8:05:23 PM
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I believe that we could indeed see 14 nm design node chips in 2015. I believe that Intel and others see a clear path for multiple patterning using optical lithography at 14 nm. But because this approach is so expensive chip companies are looking for cost reductions elsewhere - such as the economy of scale of switching to 450 mm wafers to help offset the increased expense of lithography. The bigger question is will those companies be able to make any money on those chips?

any1
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re: TSMC says equipment vendors late for 14-nm
any1   9/8/2011 8:15:31 PM
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I would speculate that optical lithography with multiple patterning and all the other process tricks and advanced layout schemes could get us down to about 11 nm. If EUVL is not more capable and cost effective by then we will see the effective end of Moore's law.

chipmonk0
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re: TSMC says equipment vendors late for 14-nm
chipmonk0   9/9/2011 6:52:39 PM
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The message here is that TSMC does not have what it takes to go to 14 nm on its own. Its waiting for Intel to figure it all out and then once again will get the technology free via the equipment suppliers ( as happened with ALD for gate last HKMG ) - albeit 2 years later. What if Intel now decides to do a lot more of the tool development for future nodes in - house and thus crush these bottom - feeding pretenders ?

resistion
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re: TSMC says equipment vendors late for 14-nm
resistion   9/11/2011 2:54:22 PM
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No company can go purely on its own anymore. At least lithographically, Intel's risk is reduced by memory makers esp. NAND flash like Micron and Toshiba. They validate existing lithography tools can go down to 1X nm. Logic half-pitch is actually a generation behind NAND flash. As for high-k, some may question if it really is advantageous. Qualcomm for example, skipped on high-k at 28 nm. And Atom power consumption is still considered pretty high. So if tsmc bet all on high-k like Intel, that would have been an instance where it would have been wrong. The newest development is the finfet or multigate, which Intel showed at 22 nm. But this technology was already available years ago. Intel should get credit for reducing the risk of transitions like these. But these transitions for Intel are for only one type of product, x86 microprocessors, which hardly applies to memory makers or fabless/foundries.

rfab
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re: TSMC says equipment vendors late for 14-nm
rfab   9/12/2011 1:55:29 AM
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Atom power and design more relevant, because the X86 complicated than ARM

Pushkar Ranade
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re: TSMC says equipment vendors late for 14-nm
Pushkar Ranade   9/13/2011 9:05:33 PM
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TMSCís warning about cost/complexity of EUV at 14nm and delays in the 450mm transition supports a growing pool of evidence that the 28/20nm nodes will be in production much longer than historical life cycle. This suggests that device-level innovation will need to continue on the planar transistor platform into the foreseeable future. Foundries and design houses alike will seek to enhance power/performance trade-off and try to maximize product level benefit from 28nm/20nm technologies. A 14nm technology is certainly physically achievable, but its likely going to be limited by cost/economics.

krisi
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re: TSMC says equipment vendors late for 14-nm
krisi   9/13/2011 9:10:58 PM
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Exactly my thinking Pushkar, there is a big difference between technology feasability and economical volume production, a distinction that some commentators above seem to neglect...Kris

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