SAN FRANCISCO—As expected, IBM Corp. and 3M Corp. announced Wednesday (Sept. 7) that they will work together to develop adhesives that can be used to stack up to 100 separate chips in dense "silicon towers."
According to IBM (Armonk, N.Y.) and 3M (St. Paul, Minn.), such stacking would allow processors to be packed tightly with memory and networking into a "brick" of silicon that could create a chip that operates 1,000 times faster than today’s fastest microprocessor.
Under the agreement, IBM will draw on its expertise in semiconductor packaging processes, and 3M will provide its expertise in developing and manufacturing adhesive materials, the companies said.
The joint research between IBM and 3M appears to be pursing chip stacking on a much grander scale than anything to date in the semiconductor industry. However, the companies did not describe any progress on the research, which apparently is in its infancy. No timetable was given for the development of any commercial products.
The companies say their work can potentially leapfrog today's current attempts at stacking chips vertically in 3-D packaging. The joint research will tackle some of the most difficult hurdles to the move to 3-D chips, including thermal dissipation. The research will focus on developing new adhesives that can efficiently conduct heat through a densely packed stack of chips and away from heat-sensitive components such as logic circuits, the companies said.
Equating current packing processes—which require packaging and bonding techniques that can only be applied to individual chips—to "frosting a cake slice-by-slice," IBM and 3M said the adhesives they plan to develop will be capable of hundreds or even thousands of chips at a single time.
"Today's chips, including those containing '3-D' transistors, are in fact 2-D chips that are still very flat structures," said Bernard Meyerson, VP of research at IBM. "Our scientists are aiming to develop materials that will allow us to package tremendous amounts of computing power into a new form factor—a silicon 'skyscraper.' We believe we can advance the state-of-art in packaging, and create a new class of semiconductors that offer more speed and capabilities while they keep power usage low—key requirements for many manufacturers, especially for makers of tablets and smartphones."
Intel Corp. has said it would be in volume production of 22-nm chips with 3-D transistors, or what the firm calls tri-gate transistors, by the end of this year. Various other efforts are underway to develop 3-D chips, including those that use through silicon-vias.
@RobDinsmore: I assume you are commenting on Intel's trigate technology (monolithic 3D) but Intel has also done pioneering work on 3D stacked chips starting 2002! It is true the marketing folks get carried away with what is realistic with all these new technologies but I wouldn't lower that to the BS-level!
@daleste: I agree, it is a challenge to develop materials for joining substrates, providing thermal pathways matching the conductivities of Silicon but therein lies the problem. There aren't too many gap filling materials with particle sizes in the order of a few microns. There are some promises in some emerging nano-particle based adhesives that the printed electronics industry seems to be forging ahead with (3M has a good presence there).
Dr. MP Divakar
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.