SAN FRANCISCO—Claiming an industry first, programmable logic vendor Altera Corp. said Monday (Sept. 12) it demonstrated a new floating-point digital signal processing (DSP) design flow using FPGAs.
According to Altera (San Jose, Calif.), the company's floating-point DSP compiler is the industry's first model-based floating point design tool that allows the implementation of complex floating-point DSP algorithms on an FPGA. Altera said independent analysis conducted by Berkeley Design Technology Inc. (BDTI) validates the high performance, efficiency and ease of implementing floating-point DSP designs in Altera's Stratix and Arria FPGA families.
"Using Altera's high-level DSP model-based flow, designers can implement and verify complex floating-point algorithms more efficiently and quickly than would be possible with traditional HDL-based design," said Vince Hu, vice president of product and corporate marketing at Altera, in a statement. "Once the algorithm is modeled and debugged at a high level, the design can be easily synthesized and targeted to any Altera FPGA."
Altera's floating-point DSP design flow includes the floating-point DSP compiler, which is integrated into the company's DSP Builder Advanced Blockset, Quartus II RTL tool chain and ModelSim simulator, as well as the Matlab and Simulink tools from MathWorks to simplify the DSP algorithm-implementation process on FPGAs, Altera said.
The floating-point design flow combines and integrates the algorithm modeling and simulation, RTL generation, synthesis, place and route and design verification stages, Altera said. According to the company, the flow is suited to the linear algebra problems typically requiring the dynamic range offered by floating-point DSP. BDTI benchmarked a parameterizable floating-point matrix-inversion design, Altera said.