SAN FRANCISCO – Intel gave its first public disclosure of Ivy Bridge, its first 22nm processor family at the Intel Developer Forum. The chips boast significant improvements in on-board graphics, overall performance and a handful of stepwise advances in power management and security.
Intel has long been criticized by rivals AMD and Nvidia for relatively low performance graphics cores used in its chip sets and processors. With Ivy Bridge "we have our foot on the gas, and I would say the gap is closing quickly--in a couple years the gap may be on the competitors' side," said Tom Piazza, an Intel fellow who helped design the graphics cores.
Ivy Bridge graphics support Microsoft's Direct X 11 graphics APIs, an area where Intel parts used to lag a generation. They also add support for three simultaneous displays and an L3 cache.
Among the few specific numbers Intel revealed, the graphics support 32 times more scatter/gather operations than the current Sandy Bridge chips, a fact that drew spontaneous applause from one attendee. By increasing thread counts and moving to issuing multiple threads in parallel, the cores now support twice the instructions per cycle, Piazza said.
The core is the second to be built on Intel's leading edge process. Previous graphics cores lagged the latest process by one or two generations.
As for media support, Intel revealed the current Sandy Bridge chips can decode in hardware up to 20 high def video streams simultaneously. They also boosted real-time transcoding speeds five fold over the prior Westmere generation.
Without providing hard numbers, Intel said it enhanced video performance of the Ivy Bridge cores in at least two ways. Designers boosted media sampler throughput for better scaling and filtering and added new color and contrast enhancements to the pixel-processing at the back end of the process.
The media blocks also added support for encoding using the multi-view codec, key to support for stereo 3-D.
Overall, the 22nm process with its tri-gate FinFET transistors delivers twice the performance or half the power compared to 32nm Sandy Bridge chips, said Varghese George, a senior principal engineer.
Intel added to the chip a digital random number generator that meets key ANSI and FIPS security standards. It also added a capability to prevent security attacks based on a process requesting an escalation of privileges.
For power management, Ivy Bridge can shut off I/O power to DDR memory in deep sleep states. It can also automatically route threads to the most power efficient core and optimize voltage use to the most optimal level.
Ivy Bridge supports both DDR3 memory and the new DDR3L low power chips. In addition, it allows over-clocking in 200 MHz increments without resetting BIOS, including over-clocking memory up to 2,800 MT/second.