LONDON – While many experts have expressed doubts about the ability of flash memory to scale and indicated the need for an alternative non-volatile memory technology, Hynix has just gone ahead and produced a 15-nm NAND flash memory cell which it plans to unveil at this year's International Electron Devices Meeting (IEDM).
However, at the same conference Hynix is due to report on an 84-nm pitch memory process for the production of 1-Gbit phase-change memories and beyond. As memory process are usually denoted by the half-pitch that is effectively a 42-nm process.
IEDM is due to take place December 5 to 7 in Washington DC and Hynix looks set to be a star of the conference, at least in terms of memory. Although the final program has not yet been posted, the organizers have tipped as highlights both the NAND flash and PCRAM papers that Hynix researchers are due to present. In the case of PCM whether this star status simply results from the likes of Samsung and Micron scaling back research waits on the release of the full program and the fullness of time.
Last year's IEDM saw the unveiling by Intel and Micron Technologies of the world's first NAND memory built using 25-nm design rules, which introduced the unusual technology of an air-gap to reduce word-line to word-line capacitance.
This year, Hynix Semiconductor researchers have demonstrated a NAND flash memory cell with a geometry somewhere in middle between 10- and 19-nm. At this level of miniaturization it becomes hard to measure the geometry and variability is high. According to the organizers the mid-1X-nm NAND flash memory has "excellent electrical characteristics and reliability" and the memory includes a word-line air-gap. What is not yet clear and will hopefully be included in the paper is the endurance cycling performance. As geometries decrease there is a tendency for NAND flash memory to show lower endurance significantly below the 10^6 cycles that were frequently specified at geometries above 100-nm.
Hynix is also due to present on a process technology for phase-change random access memory plus a 1-Gbit PCRAM implemented in the process. The technology is said to be highly scalable and low-cost, and was used to monolithically integrate a 1-Gbit PCRAM having 4F2 84-nm pitch memory cells occupying 0.007 square microns.
Surprisingly the memory technology is said to have 10-year data retention at temperatures above 200 degrees C. Such robust thermal stability has proved difficult for phase-change memory in the past but is critical for multilayer cell-stacking architectures.
Transmission electron microscope photographs showing cross-sections of phase-change memory cell in 42-nm process and the core/periphery areas.
Paper 3.3 is Highly Productive PCRAM Technology Platform and Full-Chip Operation Based on 4F2 (84-nm pitch) Cell Scheme for 1 Gb and Beyond, S. Lee et al, Hynix Semiconductor. Paper 9.1 is A Middle-1X-nm NAND Flash Memory Cell (M1X-NAND) with
Highly Manufacturable Integration Technologies, J. Hwang et al., Hynix
Dr. Neale, thanks for the info. Many attempts to bring PCM retention to a higher level by using a material other than GST have fallen short. We also have to remember the high resistance state decreases resistance with temperature.
Regarding the Hynix patent app. The first AgLnSbTe is likely a typo. Paragrapgh 0036 under Detailed description reads AgInSbTe. You had me looking to see if there was an indication of which Lanthanide they were using. There is some research that suggests doping the chalcogenide with various of the Lanthanides will mitigate the problems with thermal stress and migration.
Resiston –Ahead of the IEDM 2011 paper your reservations re PCM elevated temperature data retention might find an answer in a recent patent application from Hynix (US2011/0193046A1). As well as the usual broad-brush material composition claims, one material composition is cited as of particular interest, AgLnSbTe.
That same patent also discloses a matrix isolation fabrication technique using an SOI structure, allowing two diodes in parallel to share the reset current and so alleviates the current density problem in the silicon. The need for this suggests the current density in the PCM cell remains high.
For me this raises the question as to the immunity of any new material from element separation associated with high current density and electrochemical effects. To be credible the claimed elevated temperature (200C for 10 Years) will need to be supported by solid evidence as a function of write/erase lifetime and in a fully processed device matrix.
The language of the abstracts “describe a complete technology platform” and data published to date suggests that this 1G-bit device may be relegated to demonstration status rather than announced as a commercial product; as the three 1G-bit PCMs (Numonyx/Micron/Samsung) that have gone before. IEDM 2011 and post-IEDM will be an interesting time for PCM followers.