LONDON – Researchers from IBM are due to report on the fabrication of a 2-GHz frequency doubler RF circuit in a CMOS-compatible manufacturing process technology at the upcoming International Electron Device Meeting, due to be held in Washington DC, Dec. 5 to 7.
Graphene, which is a honeycomb lattice of carbon atoms in a single-sheet, demonstrates not only an electric field effect but also ballistic electronic transport. The electron mobility of graphene is higher than that of silicon by at least a factor of 40. While the exceptional properties including high current density, mobility and saturation velocity make the material attractive for high performance circuits, working with carbon is difficult and is known to problematic when introduced into a wafer fab, and the state-of-the-art has been single devices and simple integrated circuits.
IBM's paper is set to move that on towards a maufacturable technology based on CMOS-compatible fabrication on 200-mm diameter wafers, according the abstract released by the organizers.
Because all the carbon chemical bonds are used within a perfect graphene sheet it has an inherently inert surface making the fabrication of a dielectric layer above it – to insulate the gate – difficult. IBM's approach has been to invert the usual manufacturing process and define gate structures first on silicon wafers and then transfer graphene layers fabricated using chemical vapor deposition to the silicon. After defining the areas of graphene IBM was able to attach source and drain contacts to the graphene to complete FET structures.
The frequency doubler integrates multiple field effect transistors and radio frequency passives and demonstrated a conversion gain of approximately -25db at an output frequency of 2-GHz, according to data released by the IEDM organizers.
Cross-sectional scanning electron microscope micrograph of the post-CMP wafer showing the inverted-T gate structure described in the paper.
The four images show: (a) an 8-inch graphene FET wafer; (b) single die; (c) SEM image of a typical fully processed device and (d) an enlarged view of the device showing the embedded gate structure with two-finger design. Except for the CVD graphene transfer, all processing was done in a conventional 200-mm wafer fab.
Paper 2.2, Graphene Technology with Inverted-T Gate and RF Passives on 200-mm Platform, S. Han et al., IBM
i agree, but this article sounds more like any research paper. The only comment about the move to manufacturing is,"IBM's paper is set to move that on towards a maufacturable technology based on CMOS-compatible fabrication on 200-mm diameter wafers."
re: "...define gate structures first on silicon wafers..." All that SiO2 (insulator) in the illustrations -- wonder if they're doing this work starting on SOI wafers -- does anyone know? (I know they do currently have a very successful RF/CMOS foundry offering that does start on SOI wafers -- see http://www.advancedsubstratenews.com/2007/10/rf-all-in-one/ ....)
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It is exciting to see graphene moving from theory to reality. Since carbon is available in unlimited quantities, will graphene circuits have environmental benefits also in terms of reduced usage of rare and toxic materials in electronics fabrication?