SAN FRANCISCO—Fujitsu Semiconductor Ltd. has adopted Cadence Design Systems Inc.'s signoff for design-for-manufacturing (DFM) technologies for its 28-nanometer ASIC and system-on-chip (SoC) mixed-signal designs, Cadence said Monday (Sept. 19).
According to Cadence (San Jose, Calif.), the DFM flow helps ensure high yield, predictability and a faster path to silicon realization. The Cadence end-to-end digital and analog deliver DFM in-design technology within the company's Virtuoso custom/analog and Encounter digital flows.
"After an extensive evaluation of all vendors in the market, we selected the complete Cadence DFM set of technologies for our most advanced ASIC and SoC designs," said Hiroshi Ikeda, director of the system LSI technology and design platform development department at Fujitsu, in a statement.
Following comprehensive benchmarking, Fujitsu selected the Cadence Litho Physical Analyzer, CMP Predictor and Litho Electrical Analyzer for 28-no in-design physical signoff and variability optimization for its ASIC and SoC designs, Cadence said.