LONDON – Scott Thompson, chief technology officer of startup SuVolta Inc., will provide an overview of advanced transistor technologies at the ARM TechCon, which takes place Oct. 25 to 27 at the Santa Clara Convention Center in Silicon Valley.
On Oct. 25 Thompson will compare FinFET, SOI, and planar bulk technologies at the 22-nm node and below.
SuVolta (Los Gatos, Calif.) recently announced its Deeply Depleted Channel (DDC) transistor technology and PowerShrink low-power CMOS platform, which the company claims reduces IC power consumption by 50 percent or more while maintaining circuit performance.
The novel DDC transistor structure enables reductions in both the supply voltage and of the transistor size to the sub-20nm node while maintaining compatibility with established fabs and design techniques, according to SuVolta.
The technology would appear to have similar characteristics to fully-depleted silicon-on-insulator (FDSOI) without the extra cost of FDSOI wafers. SuVolta is working with Fujitsu and other semiconductor companies to realize its technology in leading-edge manufacturing process technologies
SuVolta, formed in 2005 under the name DSM Solutions Inc., is a member of the Silicon 60, EE Times' list of emerging technology startups.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.