LONDON Ė Resistive RAM, a non-volatile memory technology usually based on metallic oxide, is unlikely to enter the market until after the 11-nm node, according to Laith Altimime, director of the memory research program at the IMEC research institute. It may do so then as a replacement for stacked floating-gate NAND flash memory and be pushing toward the monolithic integration of 2- to 4-Tbits he said at press event hosted by IMEC.
Altimime presented a flash memory roadmap that shows conventional floating-gate flash changing to so-called SONOS flash with a vertical 8-layer stacked structure at 17-nm. The stacking could increase to 16 layers at 14-nm to 11-nm. Only after that would Resistive RAM (RRAM) enter the market when it would necessarily have to have a similarly stacked structure to allow it to compete. SONOS is a silicon-oxide-nitride-oxide-silicon form of non-volatile flash memory.
IMEC is working collaboratively with major memory manufacturers including Elpida, Hynix, Micron and Samsung on both flash and follow-on memory roadmaps. Toshiba is a notable absentee from the program. The proposed memory transistor stacking is monolithic and would be in addition to die stacking that might also be done on packaged component basis.
RRAM needs to aim at intersecting with the stacked flash roadmap after the 11-nm node, according to IMEC
For RRAM IMEC is homing in on a hafnium/hafnium-oxide based material sandwiched between conventional contacts. Altimime said that in earlier work the research had surveyed the materials but what was now emerging was a very precisely engineered layered structure that optimized dc/ac electrical performance and good R-off to R-on ratio. IMEC also feels it has a very good understanding of the switching mechanism which is related to the movement of oxygen vacancies in the crystal lattice.
At the VLSI Technology Symposium in June a team of researchers from IMEC presented an analysis of RRAM filament properties in SiO2/HfSiO/NiSi material showing how the minimal achievable current in the high resistance state depends on the nature of the filament, quantifiable through a quantum mechanical conduction model.
At the upcoming International Electron Devices Meeting due to be held in Washington DC, IMEC researchers are set to present a HfO2-based RRAM cell less than 10-nm by 10-nm, featuring the Hf/HfOx resistive element and a switching energy per bit of 0.1-pJ or lower. The endurance is reported as 5 x 10^7 cycles. However, IMEC has not done large array or stacked RRAM work. "What we deliver to the partners is the understanding. Each company then does it own chip design," said Altimime.
Do hard drives use flash much during everyday operations? They obviously have RAM caches but if you use them hard, reading/writing every bit repeatedly, e.g when recording pro video, they seem to 'wear out' quite quickly. Now I am wondering if there is some flash NV RAM used in the metadata and defect management that is getting thrashed due to the heavy drive activity?
The Life of the memory will be problem in RRAM as it is directly related with the property of the material and that will deteriorate with the usage. The life or the data retention capability of memory is the greatest factor behind the acceptability of any memory device.
Very true, in 3D Flash, the silicon body is no longer a blanket substrate but a long narrow (highly resistive) polysilicon nanowire. The voltage drop along the polysilicon channel wire (vertical or horizontal) will cause new operational complexity and incur cost previously not accounted for.
The vertical NAND SONOS architectures such as BiCS, pBiCS and TCAT have interesting challenges associated with them, namely (1) Disturbs during read since a relatively high voltage needs to be applied to all (but one) cells in the string while reading the one cell and (2)Vanishing string currents in the worst case condition when all cells are in the high threshold voltage state except the one being read. For those interested, there is data at http://www.schiltron.com/WhitePapers.html