LONDON Ė Processor IP licensor ARM and foundry TSMC have announced the competion of the design of an A15 processor test chip targeting implementation in a 20-nm manufacturing process technology.
The companies said they moved the test chip design from RTL to "tape-out" in six months, usuing a design flow co-ordinated by TSMC. The companies did not state how long the design would take to be instantiated successfully in 20-nm silicon, which at TSMC is a planar process. Nor did the companies indicate whether the design is single-core, without peripherals, or whether it is a full working multi-core processor suitable for use in applications.
ARM said it would now optimize its physical IP to the TSMC 20-nm process for power, performance and area and produce a specification for a Cortex-A15 processor optimization pack (POP). It did not say how soon this would be completed.
"This first 20-nm ARM Cortex-A15 tape out paves the way for the next generation of SoC integration and performance," said Mike Inglis, general manager of ARM's processor division, in a statement. These SoCs will be suitable for smartphones, tablet computers, digital home systems, servers and wireless infrastructure, ARM said.
Separately Cadence Design Systems Inc. (San Jose, Calif.) said that engineers that it employs also helped with the design and that it used a Cadence RTL-to-sign-off design flow that was the result of 18 months work between ARM and Cadence.
ARM makes use of Cadence tools for design work and the two companies are working to optimize ARM processors and Cadence design flows so they work well together, Cadence said.
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