LONDON – Processor IP licensor ARM Holdings plc has revealed a power efficient Cortex-A7 processor core that it says is intended to be used alongside its top-of-the-range Cortex-A15 as part of a heterogeneous power-driven multicore strategy.
The A7 is a dual-issue, eight-stage pipeline core that has been heavily optimized for power efficiency, but supports the same virtualization and extended addressing as the A15. As a result ARM (Cambridge, England) expects partners to implement a "little dog, big dog" strategy so that cores are selected to run applications based on power efficiency needs.
Alternatively, the A7 processor can be used in single- or dual-core instantiations stand-alone to power an entry-level smartphone for price sensitive markets, ARM said.
Warren East, speaking at the U.K. launch of the A7, said that he expected multicore chips, which could be dual-core A15 plus dual-core A7, to be in the market and powering smartphones in 2013.
The "big-little" strategy allows low-performance basic and always-on tasks to be run on one or more A7 cores, to maximize battery life, while tasks requiring greater performance would migrate to the A15 cores. This dynamic core selection can be made transparent to the application software and middleware running on the processors, supported by advanced ARM system IP, such as AMBA 4 ACE Coherency Extensions. The movement of tasks between paired A7 and A15 cores is triggered by the same system that drives the dynamic voltage and frequency scaling that has become traditional in leading-edge system chips, the company said.
A coherent "big-little" system-chip based on internal dual-core A7 and A15 processors
In a 28-nm process the A7 is less than one fifth the size of the Cortex-A8 in a 45-nm process, while providing greater performance and much greater power efficiency, the company said. A dual-core A7 processor in 28-nm would produce about a 70 percent power saving compared with a dual-core A9 processor implemented in 40-nm. In other words it will consume about one-third the power.
ARM had two or three lead partners on the development of the A7 and the associated big-little strategy, East said, but he declined to name them individually. ARM now has a wave of semiconductor licensees eager to use the A7 core. Broadcom, Freescale, HiSilicon, Samsung, ST-Ericsson and Texas Instruments are listed as supporting the technology along with system and software companies Compal, LG Electronics Linaro, OK Labs, QNX, Redbend and Sprint.
"We took the A15 to market last year because we needed to push the performance envelope. But power efficiency is the most important thing for ARM. The A7 is the most efficient core yet," said East. Tom Cronk, deputy general manager of the processor division at ARM said that power efficiency driven selection of resources has been used before, for example in the area of graphics but not for general purpose processor cores.
The Cortex-A7 processor occupies less than 0.5 square millimeters, using a 28-nm process technology, and provides useful performance at about 1.2-GHz clock frequency in both single and multicore configurations. Used as a stand-alone processor, the Cortex-A7 will deliver sub-$100 entry level smartphones in the 2013-2014 timeframe with an equivalent level of processing performance to today’s $500 high-end smartphones, ARM said.
While A7 is aimed initially at smartphones East said he was sure the big-little strategy was applicable in other areas. East said he expected power-driven resource allocation would subsequently be deployed in consumer electronics and any area where complex processing also met a need for power efficiency.
Tape-outs including the Cortex-A7 are expected in the first half of 2012 with SoCs and products based on them to follow in 2013, East said.
Yes it is quite true why a designer will host two different chips and going on switching applications between both of them, instead multiple cores will be better option, the power concern can be handled by turning on and off the cores dynamically.
Tools vendors will have their hands full with all the derivative cores. MIPS did this a while back with incompatible cores. As it is, every six months there is another ARM core, with their CMIS standards etc. If one A15 and one A7 core is run in the above diagram, the cache split will be interesting, and what about tracing this lot? How does the core decide what load to run? Surely the developer has to specify this. The comparisons of different cores at 45 and 28nm is misleading. Will be interesting to see how this takes off against NVidia, iMX6000 and other multi-core vendors with identical cores.
Not saying how important of the numbers of multi-core technology, ARM still has long way to go to deploy superior multi-core solution, like efficiency of ACP to improve I/O performance and Virtualization ...etc. Compare to ARM, MIPs IP price is far cheaper but eCosystem and power efficiency are also weak.
I've seem lots of me-too product with ARM solution in the market for specific regions, especially, China, Taiwan and Indian deploy similar Network and Media SoC in the market. That says, ARM is the winner of IP biz and leave the product competition to the chip design house.
For power efficiency, ARM do the best. It is its key competition. In China, more and more companies start to use ARM architecture IC with embedded Linux to develop products. The ARM core IC has the most large share market in China. It is also my first choice to make the new project.
Add in a graphics co-processor and you have little, big, bigger. It's an interesting approach and does make sense. With the graphics co-processor architecture, high-power functions are offloaded from the main processor. With this approach, low-power functions are off loaded from the main processor.
My understanding is that for identical cores On a chip ARM does offer a slight discount...this would drive down the royalty rate per core if ARM was not able to drive up the base rate!
ARM can try and do that by arguing that newer cores have increased functionality, performance. licensees can resist by saying that too higher royalty rate will make them look elsewhere!
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.