SAN JOSE, Calif. – The widely used PCI Express printed-circuit board interconnect will double its data rates to support up to 16 GTransfers/second in an upcoming version 4.0. The PCI Special Interest Group hopes to complete the spec by the end of 2014 and first systems using it could ship in 2016.
PCIe 4.0 is expected to be the group's last standard based on copper. Given the group's traditional four-year cadence between releases, a revolutionary shift to optical board-level interconnects could begin in earnest about 2019.
The PCI SIG has not completed work to determine detailed requirements for the spec. However members believe the 16 GT/s speeds probably will require at least two or three levels of decision-feedback equalization, also known as DFE taps.
Designers needing to support current maximum distances covering 20 inches and two connectors probably will need re-driver chips. One PCI SIG member said any board using PCIe 4.0 over distances greater than ten to twelve inches and including one connector will likely require re-drivers.
The group expects the faster speeds to open doors to lower power systems. Many current designs use multiple PCIe lanes in parallel to meet their throughput needs at the cost of more wires and I/O pins and thus higher power use and larger chip packages.
"We expect that ultimately PCIe 4.0 will be adopted by anyone doing a by-four or by-eight PCIe 1.0 design today," said Al Yanes, president of the PCI SIG.
Traditional bandwidth-hungry applications such as high-end graphics and networking are expected to be among the first users of the technology. In addition, flash drives may be quick to adopt PCIe 4.0 for performance advantages, Yanes said.
Version 4.0 will use the same 128b/130b encoding as the current 8 GT/s version 3.0. Thus it should have similar overhead for applications-layer throughput. The first two versions of PCIe used 8b/10b encoding, and thus had lower processing overhead.
PCI SIG members spent six to nine months running simulations, mainly focused on finding out if it should target 16 or 24 GT/s for what the group assumes will be its last copper-based spec.
"We did enough work to know 16G is optimal and we can execute a spec at 16G, [but] there wasn’t anything optimal beyond 16G," said Yanes. "It became too technically challenging to achieve anything beyond 16G—24G [would] blow out the jitter budgets, and you have to have enough margins to do this in high volume manufacturing," he said.
"At the end of the day, we want PCIe to be a low-cost copper solution and be backward compatible," he added.
Plenty of details have yet to be worked out for PCIe 4.0. Much of the emphasis is on finding ways to save active and idle power.
"You want to keep lowering power utilization numbers to give yourself options of proliferating the technology into new opportunities," said Yanes.
So far, the PCI SIG has only one active effort on optical. A working group developing a cabled PCIe Version 3.0 specification that could compete with Thunderbolt has been charged to consider an option for an optical medium.
The cable group has been formed and is holding weekly meetings. However it may take until early next year before it is ready to report what specific goals it has set, said Yanes.
"Optical will be a revolutionary change" when it comes, said Yanes.