LONDON – European chip company STMicroelectronics NV has said it has produced the first wafer on which the die were fully tested wirelessly and without the use of contact probes.
The electromagnetic wafer sort (EMWS) technology was applied to a wafer of RFID (Radio Frequency Identification) ICs. It was developed in an R&D project called UTAMCIC (UHF TAG Antenna Magnetically Coupled to Integrated Circuit), led by Alberto Pagani, Giovanni Girlando and Alessandro Finocchiaro from STMicroelectronics, and Professor Giuseppe Palmisano from the University of Catania.
Electrical wafer sort is the last stage of wafer fabrication prior to assembly and test of packaged ICs. Conventional a probe card connected to automatic test equipment (ATE) makes contact with the bond pads on each die in turn and runs a series of tests. Under EMWS each die contains an antenna and the ATE supplies power and communicates with the IC wirelessly.
In some applications this can remove the need for dedicated test pads and reduce die area.
ST said that limitations in the amount of power that can be transmitted wirelessly means that some ICs will still require contact probes but that EMWS was applicable to low-power ICs.
EMWS make use of a focusing technique that can use multiple antenna to concentrate electromagnetic energy from across the wafer to the a small area, such as a single die. The Electromagnetic Concentrator/Expander allows the communication distance between the die and an external system such as the ATE to be increased by at least one order of magnitude.
Contactless testing also reduces the test cycle time because it reduces wafer movement and enables parallelism. Moreover, it increases yield by eliminating the pad damage that occasionally occurs during standard contact testing, ST said.
Anyone remember Anamartic? They tried to develop DRAM arrays, but they also included on-wafer testing. They allocated some wafer tiny space to test logic that tested everything on the wafer in parallel, with a simple chained GO/NO-GO comms bus spiralling out to connections at the edge.
Time and cost saving were pretty good, probably patent issues stopped everyone using the technique. Guess it also would've meant chip designers listening to the needs of the test department, that would be a first, hey?
Easiest with digital, but some analog testing can be done, also, and since that takes much longer the benefits are greater from parallel testing.
Probably the killer was it makes step-and-repeat more difficult.
I don't see this technology going beyond RFID chips. It's a good idea to test the RFID chips they way they are used. Other devices require more power than can be provided wirelessly. They also require the bond pads and it would take up too much space to add the RF receiver to power the chip.
If pushed well ( e,g. by DARPA ) this could be the beginning of something big and may change things radically beyond just Test of simple RFID wafers. For potential check out work done at Sun before Oracle bought it.
It is had for me to see what product lines this technology would be excel on. Low power RFID chips are small, cheap and packaging dead chips can eat at already slim margins. Still, improving yield and eliminating test strikes me as the intuitive route to reducing cost on mature products. This technique would have to operate in a high GHzrange given the antenna size.
@PeterClarke: this topic has been researched for a while now and I hope the work above can be transferred to a production environment. That is where the proof lies ultimately.
Just curious, what is the time interval between the step & repeat cycles? I would imagine there has to be couple of orienting beams in the probing array to align at each die site. It would be interesting to know how long does it take for each cycles? Not to mention the overall cost of the EMWS probe card assembly.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.