SAN FRANCISCO -- JEDEC which announced a broad set of 3D IC standards development earlier in 2011 is all set to release what is touted as the first 3D IC interface standard which will be out in late December of this year (or some time in January 2012).
At GSA's 3D IC task group meeting held earlier this week, Intel's Ken Shoemaker presented more details of the WideIO Memories where more details of the electrical and mechanical interface were shared.
JEDEC has a head start in releasing 3D IC standards –its standard for reliability of 3D chip stack with through-silicon-via (TSV), JEP158, was released in Nov 2009 . With the soon to be released WideIO standard, it appears it is maintaining that lead, for now among the standards generation efforts of SEMI, Sematech and Si2.
The industry consensus is that LPDDR2 will run out of bandwidth before WideIO memories are commercially available. LPDDR3 (which is a linear evolution of LPDDR2) is expected to fill this gap by supporting higher operating frequencies while maintaining power efficiencies of LPDDR2. The 800MHz LPDDR3 will feature 50% more bandwidth than a 533MHz LPDRR2 while retaining the equivalent pin count as LPDRR2.
Figure 1. WideIO Positioning Source: Sophie Dumas, ST-Ericsson, Mobile Memory Forum, June 2011; more mobile memory presentations here
Developed by JEDEC task group JC42.6 which began its work in December 2008, WideIO is explicitly a 3D standard for now (2.5D interface is on the future development roadmap) combining logic and DRAM in the same package to reduce interconnect capacitance. The soon-to-be released specification calls for a maximum 4-dice stack of memory cube that can interface to a logic SoC with a maximum target package size of 10x10x1mm.
JC42.6 for WideIO specifies the logic to memory interface (LMI) leveraging the work of two JEDEC committees –JC42.6 (Low Power DRAMs) and JC11 which has a long-standing in mechanical standardization of chip packages. The mechanical interface between memory logic and memory has been generically named as Micro Pillar Gate Array (MPGA, link).
The interconnect method between logic and memory is not specified and can be micro bumps, micro pillars, etc. The standard also specifies boundary scan to test interconnect continuity, post-assembly direct-access memory test, location of thermal sensors in the memory dice, and the exact mechanical layout of the chip-to-chip interface.
The standard does not specify the memory-to-logic interconnect design or method of assembly. The exact location of the interconnect on either the memory or the logic chip is not specified as are the dimensions and locations of TSVs. The thickness of memory and logic chips, assembly methods and post-assembly test methods are all unspecified.
Thermal management will always be a challenge when the horizontal real estate is a premium and one is constrained by cost for adding solution in the vertical dimension!
Dealing with thermal management is an application issue that the JEDEC standard recognizes but steers clear of making specific recommendations. It is up to the design teams.
Sanjib, a good majority of the 3DIC using TSV's are & will be substrate-based packages, BGA being the most common. The biggest advantage of stacking using TSV's is by delivering much more functionality (not to mention the storage) in the same form factor.
Well, packages have been growing in the 3-rd dimenions for several years now -incarnations like Package-on-Package (PoP) are shipping in millions of volumes. Amkor recently announced crossing 100Million PoPs.
TSV's are one way to start stacking bare dice to realize a product. 3DIC stacked products look much like existing Semi packages while internally their construction will be a lot different.
The interface defined by the JEDEC WideIO standard lets one create memory+controller product by stacking. It doesn't dictate the dia of TSV's but provides guidelines for locating interconnects between memory, logic and other functions via TSV's.
I hope this helps.
Does it mean that after the standardization of the 3D IC, memories packages will get converted in to cube forms instead of stripe packages? If the interface is planner as depicted in the figure, why it is called 3D IC?
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.