Figure 1. WideIO Positioning
Source: Sophie Dumas, ST-Ericsson, Mobile Memory Forum, June 2011
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Developed by JEDEC task group JC42.6 which began its work in December 2008, WideIO is explicitly a 3D standard for now (2.5D interface is on the future development roadmap) combining logic and DRAM in the same package to reduce interconnect capacitance. The soon-to-be released specification calls for a maximum 4-dice stack of memory cube that can interface to a logic SoC with a maximum target package size of 10x10x1mm.
JC42.6 for WideIO specifies the logic to memory interface (LMI) leveraging the work of two JEDEC committees –JC42.6 (Low Power DRAMs) and JC11 which has a long-standing in mechanical standardization of chip packages. The mechanical interface between memory logic and memory has been generically named as Micro Pillar Gate Array (MPGA, link).
The interconnect method between logic and memory is not specified and can be micro bumps, micro pillars, etc. The standard also specifies boundary scan to test interconnect continuity, post-assembly direct-access memory test, location of thermal sensors in the memory dice, and the exact mechanical layout of the chip-to-chip interface.
The standard does not specify the memory-to-logic interconnect design or method of assembly. The exact location of the interconnect on either the memory or the logic chip is not specified as are the dimensions and locations of TSVs. The thickness of memory and logic chips, assembly methods and post-assembly test methods are all unspecified.