SAN JOSE, Calif. – DSP specialist Ceva Inc. will demo at CES the first of a new family programmable vision processing cores handling gesture and face recognition. The MM-3101 can handle eight MPixel images at 12 frames per second, using with as little as 20 times less power than an ARM Cortex A9 on some jobs, the company claims.
The MM-3101 handles up to two simultaneous threads using two vector and two scalar processing units each with its own memory access interface. The core uses an instruction set tuned for pixel processing tasks such as filters and transforms.
Ceva will show the core handling gesture recognition using software from EyeSight, a third party software vendor into which it joined with Japan's Mitsui to invest a total of $4.2 million. In one demo, Ceva will let users create a virtual cursor by moving a finger in the air.
Gesture recognition has become a hot topic for mobile devices. Nvidia, Qualcomm and Texas Instruments have all developed capabilities for their chip sets, often in concert with partners.
The Ceva core can be implemented in as little as 0.72 mm2 of silicon in a 28 nm high performance process. Ceva also supplies a suite of tools and software libraries for building vision applications.
Ceva has already licensed the core to one unnamed mobile application processor vendor in China.
The core is the first implementation of a new image-processing architecture. Future versions will add more vector, scalar and other cores to tackle a variety of applications including augmented reality, said Eran Briman, vice president of marketing at Ceva.
"There are plenty of video and front-end image processors available, but this is among the first processors architected for embedded vision," said Jeff Bier, general manager of DSP consulting firm Berkeley Design Technology Inc.
"Consumer video is very standards based particularly for codecs, but for vision apps there are no standard algorithms, so programmability is more important," said Bier who is founder of the Embedded Vision Alliance, an industry trade group.
One challenge for Ceva will be in how it strikes the balance between optimal performance versus maximum flexibility in its cores. It mus\t also prove its programming tools are easy to use, Bier said.
I suspect that this will either be a short-lived product or end up only in niche applications. The next generation of processors will likely have enough horsepower to do the same tasks in software without a significant performance hit.
This is a comment to both.Image understand tasks require 2-D area based image processing, best applied using vector processors and data-flow architectures. Doing this is SW really reduces it multiple for loop structures, which consume cycles and power. A dedicated data-flow vector processing pipeline can do it efficiently at lower power. The key is to balance the HW flexibility so that programability is not impacted
@dnandy, thanks for the interesting comments. I can understand how a dedicated hardware architecture results in better efficiency (i.e. performance improvement), but I am not clear as to how power consumption is reduced. e.g. we are comparing power consumption for gesture recognition between the MM-3101 and an ARM Cortex A9.
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