The company raised $19.1 million in 2008 and 2009. The company announced it had raised a Series B of $7.8 million in 2011. The company has 50 engineers and is backed by several French investment funds including: ACE Management, Inocap, Eurekap, CEA Investissement, Rhône Alpes Creation, Promelys, local funds and other private investors as well as by the French government agency OSEO, which provides support to startups.
Along with the chip, Kalray is offering development boards and the AccessCore software development environment, the website indicates.
AccessCore supports a C-based programming model but support also varies between different user profiles from Linux support for legacy functions up to a dataflow environment that can maximize use of the array. Standard GCC & GDB technologies are used for compilation and debug.
"Kalray's technology has been developed with many OEM partners across several vertical markets, as well as partnering with third-party software vendors," said Monnier, in a statement issued May 2011. "Our first processor achieves a global processing power of 500 billion operations per second, along with a much lower power consumption than competitive solutions. Embedded designers will get the benefit of high processing power, low power consumption and high level programming to develop innovative applications in the fields of image processing, signal processing, control, communications and data security. The access cost of MPPA processors makes them optimum for all low to medium volume applications."
The 256-processor chip allows array extension by the clustering of several chips and the I/O offering includes generations 2 and 3 of PCI Express, Ethernet able to run at up to 40-Gbits per second and general purpose I/Os. Memory controllers for flash and DDR DRAM allow for external storage of up to 128-Gbytes. And is described as being in a standard 40-mm x 40-mm BGA package.
And, as one might expect, the 256-processor chip is the first in a projected family. The MPPA family scales from 16 to 64 clusters per chip. The 1024-core version delivers up to 2-Tops [tera operations per second]. The MPPA also includes 4 to 8 Interlaken interfaces for multi-MPPA chip systems and connection to FPGAs.
Ultimately surely the general purpose model has to be similar to that used by multiple computing nodes hanging off the Internet, but writ small on a single die.
For now the likes of Intel and ARM want to keep everything coherent and synchronized but my instinct tells me that cant work as you go to scores of core except in certain very tightly controlled applications.
Plurality's HyperCore developed a many-core design not only for wireless inftastructure.
Although not successful yet in producing a maketable product, it proposed a holistic solution for programming model and hardware that programmers liked and silicon could handle.
I believe message passing for massively parallel machines is not usefull. Here is another one who tries.
Don't forget Martin Marietta with their Geometric Arithmetic Parallel Processor (GAPP) in 1988. A large circuit board held 32,000 processors as I recall. It supported a Single Instruction Multiple Processor (SIMP) approach. Great for working on images after the initial overhead of clocking in the data from an edge.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.