MOUNTAIN VIEW, Calif.--Globalfoundries CEO Ajit Manocha has praised his firm for what he called a “remarkable quarter” in Q411, and promised that the foundry was on track to “keep the momentum going,” after a year plagued with difficulties and setbacks.
Globalfoundries' new fab in upstate New York is due to start ramping imminently, he said, with 20-nm expected to be introduced in June. The company has said it expects to spend more than $3 billion in capital expenditures this year.
While that figure may seem significant, it's significantly lower than the more than $5 billion that the company spent on capex in 2011. Analysts have suggested that the decrease is largely driven by the delay (or potentially cancellation) of a new fab in Abu Dhabi.
Globalfoundries did not disclose 2011 revenues, but after its challenges with yields on AMD chips and a restrictive wafer supply agreement, there is speculation in financial circles that the firm may well have missed its 20 percent growth projection (on 2010 revenues of $3.5 billion) predicted at the beginning of 2011.
Meanwhile, Manocha said Globalfoundries’ Dresden facility would continue with 32-nm and 28-nm manufacturing, while plans were already underway for 14-nm.
In an interview with EE Times, the CEO dismissed Globalfoundries’ competition as only having shipped “a few thousand wafers” with high-k metal gate in 2011, noting that his firm had shipped well over 700, 000. “People thought that gate first would never work, but didn’t we prove everybody wrong?” he asked.
Despite Manocha’s confidence, however, many analysts still question whether HKMG was indeed the right choice to make. The struggles with gate-first HKMG were well-documented and cost companies like AMD tens of millions of dollars in lost revenue in 2011 due to the delays in launching its Llano APU.
While technically elegant, the gate-first HKMG has proved particularly difficult to ramp and now the company will need to make another challenging transition as it follows Intel and TSMC to gate-last HKMG at 20-nm.
Manocha agreed that scaling from 40-nm to 32-nm had indeed presented a challenge, and that it would be yet another bridge to cross reversing the metal gate going from 28-nm to 20-nm, a bigger challenge, he said, would likely come from the photo lithography side of the process and then moving to 450 mm wafers.
Some relevant quotes from an article "That's Two For Intel" published by Tom's hardware.
Supposedly QCOM is not even using high -k /metal gate...
Importantly, TSMC’s decision to go with gate-last (following Intel's approach) is steeped in history, according to the company’s senior VP in charge of R&D. Part of the reason why gate-first manufacturing results in low yields is that you have to control threshold voltage carefully, since the N- and P-channels use the exact same metal. The semiconductor industry tried to carefully control the voltage this way two decades ago and found it very difficult. The gate-last approach doesn’t require the same control because the metal for the P channel is different than the metal for the N channel. You lose some density, but yields are a lot higher, and the easiest way to lose a fight is to not show up at all. It’s not trivial to switch a design from gate-first to gate-last. It requires additional redesign time. To that end, you can’t just change your order from Globalfoundries to TSMC by checking a different box on a form.
It seems that Qualcomm figured out it can’t get the yields it needs on a gate-first approach. At the 2010 International Electron Devices Meeting held in San Francisco, the company stated that it wouldn’t be using high-k/metal gate technology for the majority of its 28 nm products. This is a big disadvantage for Qualcomm.
You have Qualcomm, which faces challenges on the manufacturing side due to gambling on gate-first high-k and now being forced to go with standard silicon,
He can say anything he wants but without data to back it up, it's just a propaganda to hide his real issues. maybe he does not even know what the real issues he is facing. GF lost credibility in a big time. customers will know whether he is telling us truths or not.
In order to ramp the product in 32nm and below, the fabless design house need the design expertise to show them how to modify the current design to fit the advanced process, especially for HKMG one. There are few high order effects never shown in bulk process before. GF needs someone to help AMD migrated to 28nm Gate-First HKMG technology.
Qualcomm, TI, and others did not use much high-k/metal gate technology at 28nm because of a lack of maturity at all foundries. Relatively low yields, relatively high costs, caused them to stick with a largely non-high-k gate stack at 28nm. This has little or nothing to do with gate-first, gate-last, GlobalFoundries or TSMC.
Even after the gate first fiasco GloFo keeps blindly following IBM for technical decisions. To catch up after these embarrassing ( fatal ? ) technical decisions GloFo needs people with a successful track record at the top. Yet GloFo is full of people from Motorola Semiconductor Fabs in Autin that failed to keep up and withered away into Freescale. GloFo CTO is from Motorola and does not even have a PhD. Just compare that with the TSMC bench.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.