SAN JOSE, Calif. – Avago Technologies and Texas Instruments are among the companies at DesignCon this week with new components to drive boards and cables to higher data rates over longer distances for less power and cost. They and their competitors are gearing up to enable a next-generation of systems using 100 Gbit/s Ethernet and 10+ Gbit/s interfaces.
Avago is announcing a 25 Gbit/s serdes that can support transmissions across more than a meter of a backplane and up to five meters of copper cables. It will also demonstrate a 32 Gbit/s chip, likely aimed at next-generation Fibre Channel storage networks.
Texas Instruments is rolling out a line of ten 12.5 Gbit/s signal conditioners that drive signals across copper cables over distances of up to 20 meters. The components aim to replace larger, more expensive and power hungry physical layer chips.
Both companies are using the latest process technologies and signal integrity techniques to hit new milestones. They join an industry focused on responding to the need to carry ever more data over networks while keeping a lid on power and cost.
Many of the chip, board and cable companies at DesignCon aim to enable 100G Ethernet products that use four lanes running at 25 Gbits/s. The products set to ship late this year will provide reductions in cost, size and power compared to today’s 100GE systems that use ten 10 Gbit/s lanes.
“The adoption of 100GE is happening much quicker than we anticipated with the rise of things like LTE networks and iPads,” said Sanjay Gajendra, a senior product manager at Texas Instruments. “We still believe mass production [of the next-gen Ethernet products] will be at the end of the year, but a few vendors will demo prototypes earlier,” he said.
“The bandwidth needs of OEMs are going up incredibly every year,” said Frank Ostojic, general manager of Avago’s ASIC group. “25G will require a system level approach and coordinated work in a close partnership among the board, chip and package suppliers--it will be a kind of chip-set approach,” he said.
Multiple networking and telecom companies are already designing ASICs that will tape out over the next several months with Avago’s long-reach 25G serdes. The chips comply with the latest 25G standards from the Optical Internetworking Forum and hit new lows in latency and power consumption, numbers that Avago is keeping under wraps.
“You need 28 nm process technology to make this work,” said Ostojic.
Avago’s 25G serdes, which will eventually appear in the company’s standard products, employ proprietary techniques in clocking and decision equalization feedback (DFE). Avago also is expected to demo a 100G kit that can be used to optimize designs with any vendor’s serdes including competitors such as IBM, LSI and STMicroelectronics.
TI’s signal conditioning group, formerly part of National Semiconductor, is using DesignCon to launch a line of 12.5G repeaters and retimers, saving news of its planned 25G parts for later in the year.
The repeater chips consume as little as 65 milliwatts driving a 10G channel; the retimers consume about 150 milliwatts. They are meant to serve board, copper or optical cable applications across a range of protocols including Ethernet, Fibre Channel and Infiniband.
TI uses a proprietary BiCMOS SiGe process to hit the low power figures. Algorithms on the chips measure signals and apply equalization as needed on the fly.
The company hopes its the signal conditioners will replace external physical-layer chips given ASICs are increasingly building in the serdes and protocol processing functions once handled by the PHYs. OEMs can save up to 90 percent of the power and 75 percent of the board space used by the external PHYs by taking such an approach, said TI’s Gajendra.
The PHY makers such as Broadcom and Marvell are likely to offer their own twists on integrated chips and different value propositions. Gajendra said they are still likely to drive greater power consumption.
TI must also compete with other repeater and retimer vendors such as Gennum. Both companies gave demos last year at DesignCon of 25G products in the works.
Engineers are aiming for 25G products supporting 30dB loss, said Gajendra. Products demonstrated to date hit about 25 dB, he said.
For EE Times' full coverage of DesignCon, please visit here.
25G is a incredible speed, and with the right protocol, the Data throughput could be impressive, for applications that can justify the cost/ performance trade off, keeping in-mind silicon foot print costs, Phy Power requirements, latency and deterministic end to end latency which is critical and often over looked. Also how much CPU power and cycles are needed to feed this rate, maintain Stacks for some protocols. I think we will see a quick transition from the today common 10G to 40G then to 100g chip to chip interfaces in the coming 18 months.