SANTA CLARA, Calif., EE Times is covering DesignCon in Santa Clara this week, to keep up with the innovations in high speed networking, board design, chips and testing.
The show is where engineers converge to figure out how they're going to make the next fastest thing happen, and thrash out the issues the industry is facing, for example the move from 12 Gbps to 28 Gbps and the dozens of challenges that involves, from signal integrity to power integrity.
Editor Rick Merritt also discusses the attempts to merge multiple test tools in order to make the entire testing process that much less complex.
Check out the video below and join Rick and the rest of the EE Times editorial team for more updates from DesignCon.
For EE Times' full coverage of DesignCon, please visit here.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.