SANTA CLARA, Calif. – Standards for 3-D chip stacks need to be in place within six months to stay ahead of chips rolling out in 2013, said a Qualcomm executive driving some of the efforts.
The good news is Jedec released in early January an initial standard for Wide I/O memories seen as key for mobile application processors. The bad news is some standards efforts, including faster Jedec memories needed for server and networking uses, may drag into 2013.
“We have less than a year to put the rest of the key standards in place, otherwise commercial pressures will push EDA and other companies to solve the problems themselves and want to own their solutions,” said Riko Radojcic, a director of advanced technology engineering at Qualcomm, speaking in a panel discussion on the topic at DesignCon here.
“I think we have a window of opportunity that of months,” said Radojcic who chairs a board overseeing a set of 3-D IC standards efforts underway at the Silicon Integration Initiative Inc. (Si2), an industry standards group. “Those of us who are impatient think we are already a year behind,” he said.
The Si2 effort consists of three working groups officially kicked off last summer at the Design Automation Conference. The groups are expected to deliver by the end of this year standards for the first of three phases, said Sumit DasGupta, senior vice president of engineering at Si2.
The initial phase is defining formats for sharing design data on 2.5- and 3-D partitioning and floor planning including thermal and mechanical constraints and exclusion zones between chip layers. A second phase will create formats for sharing modeling information, and a third phase will describe formats and APIs needed to create full 3-D IC design flows, he said.
The Si2 group includes participants form Cadence, Intel, GlobalFoundries, Mentor Graphics and Qualcomm among others. “Our goal is to deliver the first specs for review late in the second or third quarter,” said DasGupta.
Separately, Sematech has kicked off a variety of manufacturing standards listed on its Web site. They include definitions for process flows, thermal and mechanical strength standards and underfill materials, said Raj Jammy, vice president of emerging technologies at Sematech.
“Some standards will be done this year, some are likely to get done next year and we think the basic standards will have to be wrapped up fairly soon,” said Jammy.
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There is a "temptation" on the part of Foundries to sidestep yield issues at 28 nm by going back to say 45 nm and partition the SoCs into several layers and then connect them with TSV.
Samsung on the other hand I believe is off and running in Austin at 28 nm for A6.
@chipmonk: on the contrary, lack of real estate is one of the major drivers for stacking in smartphones.
On your last point, Micron is part of the Hybrid Memorycube consortium:
Samsung is also a (founding?) member.
@rick.merritt: assuming your'system' definition refers to a product serving homogeneous or heterogeneous functions while utilizing 2.5D/3D stacking, it will be the future of that system's design. But I would argue that that its function, whether partial or in full, must be complemented by the appropriate value addition in software. That, I believe, is the next generation of 'ASIC' startups!
I "feel" that the Apple vs Samsung tangle could turn out to be one of the biggest factors in how 3D TSV implementation and TSMC comes out in the Smartphone segment. There is a "temptation" on the part of Foundries to sidestep yield issues at 28 nm by going back to say 45 nm and partition the SoCs into several layers and then connect them with TSV. Samsung on the other hand I believe is off and running in Austin at 28 nm for A6.
Re: connecting Memory to APs by TSVs,the bandwidth needs would not become acute for a couple of years.
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