Several elements are still missing, said Liam Madden, a corporate vice president at Xilinx that announced in October a 2.5-D chip laying multiple FPGA die on a common substrate. He called for more companies to get involved in next-generation Jedec standards for Wide I/O memory running at terabit/second rates.
“The current standard is for a couple hundred Gbits/s--it’s a great start and will drive innovation in mobile, but if look at data center apps, we need another level beyond that,” he said.
According to a recent Intel presentation, Jedec has two groups working on next-generation Wide I/O standards. One group targets an eight-fold increase in the bandwidth of the initial spec with explicit support for 2.5- and 3-D stacks. A “high bandwidth memory” group is working on a follow-on standard for graphics, networking and high-performance computing, currently evaluating a 1,024-bit link, the Intel presentation said.
Among other missing pieces, Madden of Xilinx said the industry has yet to kick off an effort for stacking mixed-signal, optical and digital components. “If we are going to get to next level, that’s what I’d like to see addressed,” he said.
The industry also needs manufacturing standards for when and how work gets passed from fabs to packaging companies, Madden said. “In one example, we couldn’t send anything to anyone,” he said.
That’s a particularly thorny issue because “it’s not clear who will do much of the work and so far through-silicon via fabrication and polishing is something [packaging companies] are generally not in a position to do today,” said Jimmy of Sematech.
Radojcic of Qualcomm agreed there needs to be an effort to define how to handle stacks of analog and digital die. “Maybe analog companies need to come up with a killer app for analog-on-digital stacking, because there is nothing going on there today,” he said.
“The first thing I’d like to see is Wide I/O stuff because it drives the entire ecosystem,” said Jim Hogan, a veteran EDA executive turned private investor.
Overall, Hogan warned standards groups not to define formats too precisely.
“We don’t know how [3-D stacks] will work out,” he said. “They will become a convention after awhile, but I am trying to prevent things from becoming too complicated,” he said.
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There is a "temptation" on the part of Foundries to sidestep yield issues at 28 nm by going back to say 45 nm and partition the SoCs into several layers and then connect them with TSV.
Samsung on the other hand I believe is off and running in Austin at 28 nm for A6.
@chipmonk: on the contrary, lack of real estate is one of the major drivers for stacking in smartphones.
On your last point, Micron is part of the Hybrid Memorycube consortium:
Samsung is also a (founding?) member.
@rick.merritt: assuming your'system' definition refers to a product serving homogeneous or heterogeneous functions while utilizing 2.5D/3D stacking, it will be the future of that system's design. But I would argue that that its function, whether partial or in full, must be complemented by the appropriate value addition in software. That, I believe, is the next generation of 'ASIC' startups!
I "feel" that the Apple vs Samsung tangle could turn out to be one of the biggest factors in how 3D TSV implementation and TSMC comes out in the Smartphone segment. There is a "temptation" on the part of Foundries to sidestep yield issues at 28 nm by going back to say 45 nm and partition the SoCs into several layers and then connect them with TSV. Samsung on the other hand I believe is off and running in Austin at 28 nm for A6.
Re: connecting Memory to APs by TSVs,the bandwidth needs would not become acute for a couple of years.
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