SANTA CLARA, Calif.—Lines are blurring between the once distinct areas of digital and analog design, necessitating new tools and new ways of design collaboration, according to a panel of experts at the DesignCon 2012 conference here Tuesday (Jan. 31).
More and more, SoCs are integrating both digital and analog circuits on the same chip to gain performance and power efficiency benefits. This creates challenges for chip designers, most of whom specialize in either digital or analog design. At the same time, a number of formerly analog chips are adding digital circuitry, according to panelists from EDA and IP vendors and chip firms.
Brian Bailey, the panel moderator, set the stage by showing a slide that had previously been used by Mentor Graphics Corp. showing that 70 percent of all today's chip designs are mixed-signal. Bailey, who is also a contributing editor at EDN, said this trend was expected to continue "until there is no chip that is not mixed signal in nature." Bailey also showed data that indicates that the gap between the number of digital IP blocks and analog IP blocks coming out of major foundries has narrowed considerably in recent years.
Digital circuit design has long been viewed as the more innovative of the two disciplines. Digital has also been boosted by cutting-edge design software like place-and-route tools that automate large portions of the process. Meanwhile, automation has been lacking from tools for analog design, which requires more manual labor and is often considered something of a black art.
But the old perceptions about analog are changing as analog increasingly becomes the critical portion of many designs. "The big change today is that analog is sexy now," said Warren Savage, CEO of IPextreme.
Savage said that for the better part of the last three decades, most designers have gravitated toward digital design because it was perceived as more important at most chip companies. In the early years of his career, Savage joked, most analog designers were older people who were difficult to communicate with.
"Analog is increasingly the differentiation for devices that are being made today," Savage said. "That's where designers can make a bigger difference than they could have in the past."
Ironically, the inclination of most designers toward digital has made analog designers more valuable. In recent years, companies have talked about the difficulty in recruiting and retaining analog designers, who are a rare commodity in some parts of the world.
Jeff Miller, director of product management at Tanner EDA, acknowledged that training analog designers is more difficult than their digital counterparts. "It's not like digital, where you learn the tools and you are set," Miller said. "There is a lot of art involved in creating an analog cell. And a lot of that art is learned through hard won experience."
Miller said he has seen chip companies try to address this imbalance, attempting to train groups of designers en masse to do analog designs, often unsuccessfully. "It's a hard problem to solve," Miller said.
"Analog is such an old school discipline compared to the digital side of the ball," Savage said. "It's not easy for people to learn how to do analog design and do it really well."
But Mladen Nizic, an engineering group director at Cadence Design Systems Inc., said the renewed importance of analog design doesn't mean every digital designer is going to have to become a mixed-signal designer. Some designers who are eager to learn many different disciplines might learn how to use analog design tools, Nizic said, "but that is the exception rather than the rule."
Instead, Nizic said, the increase in mixed-signal chips needs to be addressed by greater team collaboration, with different designers bringing different skill sets to each project.
Panelists—including those from EDA vendors—agreed that analog design tools need to improve. But Navraj Nandra, senior director of marketing for analog/mixed signal IP at Synopsys, said the tools and the number of analog designers is only part of the story. "When it comes to the tools, the trick really is to understand some of the deep submicron issues that affect performance," Nandra said.
"We are making the tools more capable," Nizic said. "That's definitely what we have to do to make the designers more productive."
Many companies tried to automate the analog design flow (both schematic and layout) and failed. Things like small mismatch in the design can severely affect the performance of the analog designs. Moreover many companies are still using old-reliable analog processes and are reluctant to move to the new processes.
I would take exception to the statement that 70% of today's chips are mixed-signal. IMHO, the true number is 100%. Even (or especially) the most gargantuan digital SoC at least has a PLL or two, some DDR I/Os, and other cells that it would be a stretch to refer to as "digital."
Yes, the toolsets are very different and there is no question that the bulk of EDA innovation over the last couple decades has been on the digital side.
The really interesting part, and a big divergence of methodologies, comes at the chip top level where all the blocks get integrated.
In a Big D/Little A chip, the integration is done in a "digital" P&R tool and the analog designers just deliver their blocks (cells), however large or small -- data converters, PLLs, I/O buffers, voltage regulators or whatever. In a Big A/Little D chip, it's the other way around -- the "digital" blocks are treated as cells, like any analog cell, and the whole thing gets integrated into a full chip in an "analog" P&R tool.
To add another level of complexity and weirdness, none of the "analog" blocks are truly analog -- there are always some digital standard cells in there too. This creates interesting problems for incorporating that loose logic into scan chains and making the whole thing ATPG-tool-friendly.
The analog designers don't know the digital tools and the digital designers don't know the analog tools, so there need to be at least a few people who could rightly be called AMS designers -- those who can play in both sandboxes, to try to cobble the whole mess together into something that is thoroughly verified and tapeout-worthy.
New (ie smaller geometries) have fueled digital innovation by allowing us to pack more and more digital transistors into the same silicon area. Analog "in general" doesn't scale quite the same so going to smaller geometries doesn't make the circuit smaller and less expensive. These smaller geometry nodes also have thinner oxides and lower operating voltages so it is often more difficult to design high performance analog at these smaller nodes. That's why you hear a lot of folks saying "More than Moore" these days because a lot of really cool analog and mixed signal designs are being done at the older 0.35u and 0.18u nodes.
With the maturing of 3D-IC processing and design tool capabilities, it will be interesting to see if more companies begin migrating the analog portions to separate die/process and then integrating them vertically.
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