SANTA CLARA, Calif. – The long term future belongs to optical interconnects, low power processors and new kinds of memory architectures, said Prith Banerjee, director of HP Labs in a DesignCon keynote here.
Banerjee described the path to a terabyte/second optical bus as one step toward its vision of future systems architectures. Engineers need to embrace the new technologies to deal with the coming flood of digital data, he said.
“By 2020 your end customer will be living in a world where people access 50 zettabytes of data from 30 billion cellphones and 1.3 trillion sensors--and all that data will have to be analyzed by computer architectures you have to design,” he told a packed audience here.
Long term, HP envisions exascale computers powered by vast arrays of smartphone-class processors. They will use board- and chip-level optical interconnects and huge pools of HP’s memristor non-volatile memories, he said.
As a step in that direction, Banerjee described a 30 GByte/s optical backplane it created as a tech demo for its ProCruve 9200 switch. The backplane was built from a hollow metal waveguide bundling 12 10 Gbyte/s optical channels, costing as little as $10.
“One of the keys was the use of MEMS to do phase reflectance of the light depending on the number of taps,” Banerjee said.
He sketched out multiple techniques including using more parallel lanes with more wavelengths to deliver a terabyte/second optical backplane. “You cannot do that with copper, and that’s the disruption,” he said.
Banerjee also discussed longer term projects in areas such as silicon photonics and free-space optics that hold the promise of chip-level interfaces and photonic processing.
In a short Q&A with EE Times after the keynote, Banerjee confirmed HP’s new chief executive Meg Whitman is increasing the HP Labs budget this year. The group expects to announce in March a handful of new projects the increase will fund, focusing on integrated systems for vertical markets.
Banerjee now reports directly to Whitman rather than to retired CTO Shane Robison, another sign of HP Labs growing clout in the organization. Banerjee joined HP in 2007 as head of HP Labs and vice president of R&D.
HP is on track with partner Hynix to deliver the first commercial versions of its memristor components. They hold the promise of DRAM-like read/write performance in non-volatile storage.
“The work partnering with Hynix is going very, very well and the tech milestones are all on target,” he said.
@Netteligent: HP Labs is indeed working on the demo of an all optical bus where at each mirroring intersection, a predefined % of reflectance is captured by a MEMS mirror taking the signal to the destination. The % reflectance is set by the number of taps on the optical bus.
There were a number of things said in that keynote that are feasible but I remain skeptical about the timeline when products are likely to emerge. A number of companies have saying stuff about 1.5Trillion networked devices and this remains to be seen.
@RickMerrit: it was good to see you at the event and I enjoyed reading the report.
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