LONDON – Leading IC foundry Taiwan Semiconductor Manufacturing Co. Ltd. plans to announce 3-D IC assembly service as a general offering at the beginning of 2013, according to Maria Marced, president of TSMC Europe.
The technology is called COWOS internally, standing for chip on wafer on substrate and Marced said the company has one year to get all physical design kits and EDA support in place to allow customers to design with COWOS.
TSMC is already working with companies on the use of silicon interposer layers to carry multiple die, such as Xilinx. These "first wave" 3-D customers will be able to continue using external packaging partnerships if they choose. However, when the 3-D IC assembly service is offered TSMC plans that for most customers the 3-D assembly is done by TSMC.
A number of mobile applications processor companies, including Qualcomm and ST-Ericsson, are known to be investigating 3-D IC packaging specifically to make use of wide I/O DRAM which is expected to relieve bandwidth issues and reduced energy consumption.
Marced said that the use of multiple die in components – already commonplace in multi-chip package (MCP) memory for mobile applications – would likely change the nature of IC logic and SoC design. It would allow different functions to be developed on different optimized processes and brought together making use of through silicon vias (TSVs) created in thinned wafers. TSMC is offering a TSV-first approach to 3-D IC stacking.
Marced argued that large amounts of non-volatile memory or wide I/O DRAM could be introduced into application processors without having to include such technologies in leading-edge logic processes.
"We believe there is a good way of achieving performance while saving power and real-estate, which is advanced packaging," said Marced. Developers could stack an embedded flash device in 40-nm on an application processor in 28- or 20-nm, Marced argued.
What remains unclear is whether TSMC is prepared to assemble die from different vendors, such as memory die from specialist manufacturers as part of its 3-D IC assembly service.
It is also a possibility that this assembly transition could result in TSMC offering some standard die for inclusion in 3-D stacks as part of its portfolion of IP. "It could be that the IP goes upstream, but one thing we are very careful of is that we will never compete with our customers. We will remain a pure foundry supplier," said Marced.
TSMC has to compete against Samsung which already holds many of the cards
Samsung might come out the big winner in the 3D wars !
To gain the most ( speed, power saving, cost ) out of the pain involved in 3D TSV, co-ordination of die floor - plans for shortest interconnect length would be critical.
Samsung can control everything themselves. They already
- fab APs for Apple ( A... A6 ) now at 28 nm
- design and build their own ARM based APs
- have 40 % market share in DRAM ( down to 30 nm ) and NAND ( 20 nm )
- showed a year ago REAL 3-D memory stacks( not vaporware or computer graphics, unlike some other claims ), complete w/ bandwidth measurements & SEMs of x - section )
- builds their own substrates
Fabless wonders who depend on TSMC for high margins and market share in the Smart Phone / Tablet segment might be sweating.
TSMC will eventually win given its high volume history with big chip companies. One stop is convenient for these types of businesses and what TSMC is offering makes sense.
How ever, I don't think this bodes well for smaller companies and startups of tomorrow who can really innovate with applications and required processors enabled by 3D stacking. They may not have the volumes high enough to be even get their emails replied to by TSMC!
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