SAN JOSE, Calif. Ė Intel is sampling a communications chip aiming to win sockets from the likes of Cavium, Freescale and NetLogic in packet processing. Cave Creek is a new companion chip that together with the latest Xeon processors can handle up to 160 million packets per second of Layer 3 traffic.
The Xeon and Cave Creek pairing, known as Crystal Forest, marks an attempt by Intel to shift up into handling jobs in the so-called data plane, focused on moving bulk packets quickly. To date, the x86 has made significant inroads as a control-plane processor handling less demanding tasks supervising the operations of a communications system.
Intelís goal is to drive an expanding set of communications tasks to the x86. In 2013 or beyond, it plans to roll out another Xeon companion chip, this time targeted at DSP jobs for wireless base stations.
The future chip will come with a set of Intel signal processing libraries now in the works for handling Layer 1 baseband processing on next-generation Xeon processors. Base stations using the chips will still need some external parts such as Viterbi decoders.
Intel said Cave Creek will be in production before the end of the year. It targets a broad range of comms systems from ďsmall- to medium-sized firewalls to high-end routers,Ē Intel said in a press statement.
Specifically, Cave Creek is based on a Xeon companion chip, removing peripherals specific to servers and adding new ones for comms. The major new cores include hardware accelerators for cryptography, compression and pattern matching including fixed-string and regular expression operations.
The cores are part of Intelís so-called Quick Assist technology that includes APIs for running compression and security jobs on the Xeon x86 cores. The hardware accelerators are new versions of cores used in previous Intel chips such as the unsuccessful Tolapi SoC and Intelís IXP 2800 network processor now sold through a third party, Netronome.
In addition, Cave Creek includes four Gbit/s Ethernet MACs and support for USB and serial ATA. The 32 nm chip is sampling now and is optimized for use with the latest Sandy Bridge versions of Xeon. It can also be paired with Intel notebook chips such as the Core i3, i5 and i7 for comms systems that value low power over high performance needs.
As for supporting software, Intel said it will release a set of software libraries and algorithms called the Intel Data Plane Development Kit to help accelerate use of the x86 in high-end packet processing. Intel promised the software will deliver five-fold performance increases in x86-based packet processing.
Intelís Wind River division will make available a Simics model of the Crystal Forest platform. The model aims to help users test various configurations of the chip and start software development for it.
I could see this chip being used to offload packet processing functions from hypervisors or virtual machines. As networking is virtualized into the cloud, the packet processing requirements on cloud servers is increased. Perhaps this is Intel's admission that virtual networking doesn't compete and/or scale on x86. You still need specialized networking hardware.
Yeah, I thought about that, but it doesn't seem like those are going to be as dataplane-intensive as they are talking about here. I guess that if you throw in compression / encryption it might be a worthwhile target for a family of chips that scale to the job.
I think there will be a lot of macro, micro and pico base stations deployed in the next ten years, and Intel would love to see that shift to being an x86 app. It's not as big a market as smartphones for sure, but its significant.
It seems like a real niche market for a mass-market player like Intel. High-end switch fabrics for base stations are sexy, but they wouldn't seem to be a real volume business. You have to wonder if there is a larger market that they are using this to gain entry into at some point.
I love this comment: "Base stations using the chips will still need some external parts such as Viterbi decoders."
Um, last time I checked, nobody makes Viterbi decoder ICs anymore. That function is an IP block that one puts in an SoC.
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