MOUNTAIN VIEW, Calif.--Pushing forward into a new area for computer architecture, Intel is adopting transactional memory in its upcoming Haswell processors, taking the technology from academia into the mainstream, nearly two decades on.
Transactional memory (TM) is how Intel hopes to make its multi-core processors easier for software developers to take advantage of with parallel programming.
Multi-core processors are becoming one of the biggest challenges for modern software programmers, with ever more faster CPU cores emerging year by year, keeping pace with Moore’s law. How to take full advantage of the sheer power and performance these multiple cores bring, however, is no simple task.
Enter transactional memory, a software technique meant to simplify the writing of concurrent programs. In a paper discussing the innovation, analyst David Kanter of Real World Technologies said Intel’s implementation of TM struck a “careful balance” between what it actually provided to programmers versus the investment needed from Intel, noting that the firm had very carefully extended the existing coherency protocol to provide TM in a non-invasive way.
Kanter also lauds Intel’s hardware lock elision, calling it a “nice intermediate step” for programmers, allowing them to explore the benefits of TM without substantially rewriting their code.
“Haswell’s transactional memory is most likely a deferred update system using the per-core caches for transactional data and register checkpoints,” said Kanter, summing up his technical findings about Intel’s specific Haswell implementation of Transactional Synchronization Extensions (TSX).
“With the benefit of several implementations in hindsight (Azul, Sun's Rock, Transmeta), TSX seems to have avoided many problems,” said Kanter though he added that the success of TSX depends entirely on how well Haswell works.
Haswell is the first x86 processor to feature hardware transactional memory, but Kanter said Intel appears to have implemented it in a straight forward, logical and relatively simple fashion.
Kanter predicts that going forward, Intel will be able to further fine tune its transactional memory, with multi-versions more amenable to speculative multithreading, which focuses on using multiple hardware threads (or multiple cores) to work together and accelerate a single software thread.
“The other avenue for Intel is proliferating transactional memory throughout the x86 product line,” said Kanter, explaining that the firm’s efforts today centered mainly around mobile SoCs and the upcoming many-core Knight’s Corner.
“Transactional memory is a natural and obvious fit for future many-core products,” said Kanter, noting that Intel’s restricted transactional memory (or programming interface) is actually an easier programming model than many alternatives on the market, able to augment existing languages like C++ through libraries and extensions.
“Moreover, the potential to significantly improve scalability is incredibly attractive for a design with dozens of cores and hundreds of threads,” he added.
In the system proposed at DEC there were process transaction ID tags sent with memory requests. For example a read request would include the requester process ID along with the address or address range. This would be queued in the memory system and got to when it could. When delivering requested data the memory system would identify who requested it and the particular request.
I was hired by DEC as a Principal Engineer in early 1987 to implement a transactional memory. It was to be dual port to be shared between 2 of their XMI buses. One bus to connected to a Prism RISC and the other to their Lynx graphic pipeline.
The concept was new to me and I found it quite interesting. The project was cancelled because the graphic pipeline design could not meet performance objectives.
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