LONDON – Mapper Lithography BV has said foundry chipmaker Taiwan Semiconductor Manufacturing Co. Ltd. will receive one of the first Matrix pre-production e-beam maskless lithography systems.
This is not unexpected as TSMC (Hsinchu, Taiwan) has been using a pre-alpha 300-mm multiple-electron-beam maskless lithography platform from Mapper (Delft, The Netherlands) for process development and device prototyping. TSMC has also participated in the Imagine collaborative R&D project using a research tool installed at CEA-Leti (Grenoble, France).
In maskless e-beam lithography the radiation is not passed through, or reflected from, a mask but instead is used to direct-write to the photoresist. The use of multiple beams or scanning mirrors or arrays are intended to address this but the technology still has problems with throughput.
The Matrix maskless e-beam lithography system works with 5-keV electrons that have a wavelength of 0.02-nm, making resolution relatively easy compared with the difficulties experienced getting nanometer resolution from current 193-nm wavelength optical lithography. Extreme ultraviolet (EUV) lithography, a rival technology that operates at 13.5-nm wavelength, could in theory move to 6.7-nm to address resolution concerns.
Mapper recently announced that a first pre-production tool dubbed Matrix would be supplied to CEA-Leti after the completion of its build in 2012. Bert Jan Kampherbeek, CEO of Mapper, told EE Times: "We will install a tool at TSMC as well."
Kampherbeek said that the Matrix machine would be designed to house 13,260 e-beams and for a final 10 wafer per hour (wph) target. However, the Matrix 1.1 version being built in 2012 would use 1,326 or 10 percent of the beams for a 1-wph throughput.
"Already in the Matrix 1.1 we will have the 10-wph source and the 13,260 lens array," said Kampherbeek.
Kampherbeek said the next version of Matrix, version 10.1 would make use of the full 13,260 e-beam capability and offer 10-wph throughput. Finally a clustered version of the machine, the Matrix 10.10 would include ten 10-wph units in one main frame to offer 100-wph throughput which is widely seen to be a commercial requirement.
Kampherbeek did not say when Matrix 1.1 would be installed in Grenoble or at TSMC.
There are at least three potential suppliers of the maskless e-beam technology: IMS Nanofabrication AG (Vienna, Austria), KLA-Tencor Corp. (Milpitas, Calif.) with its Reflective Electron Beam Lithography (REBL) system and Mapper Lithography.
Forgot to mention about one point. You, guys, are attempting to discuss the expected performance parameters, but, at this point, the main question is if a production worthy PMB DW EBL tool could be created in principle.
As per my experience (and I was heavly involved in one of the biggest DW EBL programs) there is a very little chance, if any, that it may occur any time. The problems associated just with functioning of the pattern generating unit (heating, charging, contamination-induced insability,e-beam induced material transformations etc.) are so fundamentally enormous and the feathibility of finding solutions is so slim thaI do not believe it is doable, no matter how much resources will be pumped into.
We are running a long lasting discussion "Direct Write E-Beam Liitho- is it a Reality or a Wishful Dream? Well,maybe a greatly expensive dream..." on so-called Pseudo-Multi-Beam direct write electorn beam litho (http://www.linkedin.com/groupAnswers?viewQuestionAndAnswers=&discussionID=97351367&gid=1874399&commentID=93188640&trk=view_disc&ut=0IAiB-zCnAuBo1.
There is a whole bunch of critical unknowns in this approach, the main of them being the element (DPG in REBL, set of apertures in MAPPER etc.), which splits the initially large single electron beam into multiplicity (millions to get the throuput)of so-called beamlets, in a hope each of the beamlets could be independently manipulated. What is not yet realized by the Litho community (and what is kept secretn by the companies, developing the EB DW approaches, is the enormous load on these units, associated with their major functionality, which will result in their lifetime to be very short to do litho in any reasonable processing time even for a single wafer.
Same problem is associated with the exposure- the amount of energy transferred to the exposed spot is so high that the reist and probably even the substrate will be hardly withstanding it.
And final big question is associated with the devices, namely, will their elements, i.e. gates, gate dielectric, interfaces,be affected by the dense high energy (100 KeV for REBL, for example) electron bombardment.
In general, there are much more question than answers around the DW EBL. My most pessimistic comment is about the REBL at KLA: in more than 5 years of R&D and $200M ($100M from DARPA + $100M from KLA) not something even close to a litho prototype was created. Except a a thick marketing haze and PPT fanfaronade.
The NXE:3300 EUV 'HVM' tool from ASML cannot deliver 10-11 nm hp. The NXE:3100 pre-prod tool cannot deliver 14 nm hp. In fact, even 20 nm hp is not guaranteed at this point due to LER and the throughput is still lousy and cannot improve due to RLS tradeoff. The onus is on e-beam to deliver the same resolution or better at comparable throughput (10-100 wph), without any damaging effects.
I believe that the potential benefits of direct write ebeam are manifold. It could lower the initial cost barrier of fabricating a close to leading edge design. If the NRE costs are lower (no two million dollar mask set), perhaps it will encourage companies to take more chances on new designs. That might enable a business model with lower manufacturing volumes than would be possible using EUV lithography in the fabrication process. Direct write lithography allows multiple designs on the same wafer to help more quickly debug both the design and the fabrication process. TSMC knows that direct write lithography tools could occupy a valuable niche for them. So maybe it doesn't replace EUV for high volume manufacturing in the future but augments it instead.
If the final product has a 3D architecture or is some SoC, the costs on other parts with larger design rules are mixed in. And they may dominate. Since we've got a wider range of design rules, the leading edge design rule litho cost may not so matter as the timing, i.e., how smooth and fast the chips come out.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.