SAN FRANCISCO—Programmable logic startup Tabula Inc. confirmed Tuesday (Feb. 21) that Intel Corp. will manufacture the firm's 22-nm 3PLD products using Intel's 3-D tri-gate transistors.
Tabula (Santa Clara, Calif.) becomes the second programmable logic startup confirmed to be using Intel's Custom Foundry division for foundry work. In October 2010, Achronix Semiconductor Corp. announced that Intel would build its 22-nm FPGAs.
Intel dabbled in the foundry and ASIC markets for years. But the firm exited the ASIC business years ago and has never been considered a major foundry player. Some analysts have speculated since the Achronix deal was announced that the world's No. 1 chip vendor wanted to increase its presence in the foundry space, which is dominated by Taiwan Semiconductor Manufacturing Inc. (TSMC). Last year, the Reuters news service reported that Intel executives said, if given the opportunity, the company would happily manufacture higher volumes of chips for major companies such as, hypothetically, Apple Inc.
Like Achronix, Tabula is a relatively small programmable logic startup trying to compete in a market segment dominated by Xilinx Inc. and Altera Corp. Tabula's manufacturing volume at 22-nm will be extremely low in comparison to Intel's own products. Because there is a premium placed on leading-edge process technology in high-end programmable logic, which both Tabula and Achronix offer, it is likely that the idea of working with Intel is especially attractive to them.
"We felt early on as we looked at what Intel was doing on this technology node that there would be some synergy between our product and Intel's technology," said Dennis Segers, Tabula’s CEO.
Intel announced last May that it tri-gate transistors, which the company had been developing for years, would form the basis of the company's 22-nm process technology. The technology was originally supposed to be in volume production by late last year, but recent reports have indicated that Intel's 22-nm processors, codenamed Ivy Bridge, won't be in volume production until June.
According to Tabula, the Spacetime programmable fabric delivers a balanced architecture with shorter interconnects than traditional FPGAs and the ability to clock the entire fabric—logic, DSP, memory, and interconnect—at the same frequency. To do that, the Spacetime architecture uses time as a third dimension to reduce the number of components needed to implement a function and can deliver smaller, higher performance chips, according to the company.
Tabula uses TSMC to build its 40-nm ABAX products, which are currently in volume production and can operated at clock sppeds of 1.6 GHz. Seggers said the relationship with TSMC would continue on the 40-nm products. "We continue to work with TSMC on that product and we have an ongoing relationship with TSMC," Seggers said. "We have great respect for TSMC. They are the best in the world at what they do."
Seggers declined to reveal when Tabula's next-generation 22-nm devices would be in volume production. Details about the agreement with Intel were also not disclosed.
Good description in the article - it makes a lot of sense.
Most logic is synchronously clocked. Your approach seems to keep the states latched (in the virtual wires) while the logic is reconfigured to process other signals.
The reduced wiring complexity by treating time and space routing as interchangeable is very clever.
This offers a level in between standard logic (with gates performing only one function, often idle) and microprocessors (gates being re-used for different functions over time, at lower program speeds).
Wishing you the best success with it!
A useful way to think of this question of power consumption is to consider two identical functions. One implemented using 8 LUTs each operating at 200 MHz, and the second using only 1 LUT operating at 1.6 GHz. If interconnect capacitance were the same in both cases, then power consumption would be identical. Of course in a 3D device interconnects are shorter, so in fact there’s a power advantage for the second faster implementation.
Hi Kris, I like to emphasize the "damn fast in re-configuring your FPGA". Either the reconfiguation clock is very fast (1.6GHz?) or the system clock is very slow. For either case, this 3DFPGA burns much higher power than traditional FPGA's. No perfect solution here.
thank you @abismuth, fascinating technology: "By storing multiple gate configurations on chip, Tabula’s devices can completely reconfigure their fabrics up to 1.6 billion times per second"
any chance someone from Tabula would be interested in presenting it at CMOS emerging technologies event to be held in Vancouver in July? (www.cmoset.com)...I am the conference chair...pls contact me at firstname.lastname@example.org
Great discussion about how our Spacetime 3D architecture works.
If you are interested in knowing more about it you can read this very good article written by Tom Halfhill at Microprocessor Report: http://www.tabula.com/news/M11_Tabula_Reprint.pdf
If you have more questions you can also contact me directly or through our website (www.tabula.com).
You can imagine that this is like PC with disc cache memory. Theoretically, it could have much larger gate count under a small footprint. However, it affects the performance greatly, also 1.6GHz clock generates a lot of more power than expected, during this "on-the-fly" reconfigurations.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.