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AMD first to count on Cyclos low-power clock IP

2/21/2012 12:32 PM EST
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EDAperson
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re: AMD first to count on Cyclos low-power clock IP
EDAperson   3/3/2012 9:03:56 PM
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No tools are required for extracting inductance. The Cyclos IP that is provided has been characterized in your process and simulation/verification models are provided. Users don't have to extract inductance so no tools are required. And yes, designing a resonant clock mesh is very SPICE simulation intensive. Fortunately many EDA vendors have produced new SPICE simulators that have much greater capacity and throughput - so it is possible to simulate/verify a resonant clock mesh in a reasonable/timely manner.

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