PORTLAND, Ore.—The world's first integrated voltage regulators can be located on the bottom of a 3-D chip stack, according researchers at IBM and Columbia University, who recently demonstrated a silicon interposer containing the necessary magnetic inductors at the International Solid State Circuits Conference (ISSCC) in work funded by Semiconductor Research Corp. (SRC) and the U.S. Department of Energy.
By locating the magnetic inductors on the bottom of a 3-D chip stack, the demonstration showed how a voltage regulator's ordinarily bulky discrete components can be integrated into an otherwise CMOS design flow. Although the through-silicon-vias (TSVs) and other voltage regulator components were absent, the proof-of-concept demonstration shows how voltage regulators on silicon interposers can be integrated into future 3-D chip stacks.?
"What we have done at this point, is integrate the power inductors on a silicon interposer in what we call a 2.5-D stack—not true 3-D since we don't yet have TSVs," said Ken Shepard, a professor at Columbia University. "The next step, which we are already fabbing, is a full 3-D stack where the silicon interposers contains not only the power inductors, but also the power train—the transistors that switch those power inductors—enabling power to flow from the package up through the interposer, where it is converted down in voltage then sent up through TSVs to power the CMOS chip itself on top."? ?
Today voltage regulators are located on separate chips combined with discrete components that must feed printed-circuit board (PCB) traces connected to chip pins, requiring large currents to be pushed through extensive power distribution networks, presenting problems with both loss and power supply integrity. However, by switching the industry to voltage regulators located at the bottom on 3-D chip stacks, future self-regulating 3-D CMOS chip stacks will allow these high current levels at low supply voltages to be generated right at the load, improving overall energy efficiency by up to 20 percent, according to SRC.? ?
Future voltage regulators on silicon interposers also promise to provide all the various voltages required by modern processors and memory chips, as well as manage smart energy conservation techniques, such as scaling the voltage and frequency to match the current workload. The researchers claim that integrated voltage regulation (IVR) will be able to respond to the energy needs of future CMOS chips in nanoseconds, compared to microseconds with off-chip voltage regulators, enhancing the ability to balance workloads on multi-core processors with its switched-inductor voltage converters.? ?
The Columbia University effort, in partnership with IBM where the fabrication is being performed, claims that IVR could shave up to $270 million off the electricity bills of datacenters nationwide.? ?
All the details are available in an ISSCC paper entitled: "A 2.5D Integrated Voltage Regulator Using Coupled Magnetic Core Inductors on Silicon Interposer Delivering 10.8A/mm2.
By fabricating the bulky components such as power inductors (center) on a silicon interposer, future CMOS chips will integrate their own voltage regulators on the bottom of a 3-D chip stack.
The future of low-power ICs will likely be based on integrated voltage regulators, probably starting with silicon interposers like these, but eventually right on the CMOS chip itself. On the way to that dream, though, there are a lot of weigh-stations, which we detailed in our latest feature story: "5 Ways to Reduce Power of Future ICs" which you can read here: http://bit.ly/AyRmLI
Guess that is why they have the voltage regulator in the lowest chip layer so that the thermal path for dumping heat is the shortest available.
I agree about the heat problem and also what always crosses my mind when I read about 3D ICs. Not so much solving the fabrication of TSV in an economic way, the wafer bonding part or getting proper models. It's of course interesting but more of a controllable engineering challenge than a show stopper.
Thermal heat dissipation, though. That's tricky and it will be interesting to see how it's solved in practise for the multilayer devices I've seen in powerpoint slides.
Inductors of that size mean very high switching
frequency and switching losses. Meanwhile an IC
technology's interconnect sheet resistance is bad
for overall conduction losses.
With FPGAs drawing .gt. 10A these days, you're
going to throw the same current that takes chip
scale pass FETs, through a skinny long winding?
Reliably and efficiently? Yeppers.
Can be done, OK. But it looks to require a lot of
"right customer expectations". Personally I find
the integrated ferrite & package approaches a lot
more sensible. The inductor is always the pig,
and that inductor doesn't look like it can
handle a whole lot of current or clock period.
For someone whose primary interest is the fact of
2.x-D integration, though, I'm sure it's all
@dick_freebird: very relevant points! I asked a question to the presenter on how they were intending to interconnect to the next level from either the Si interposers or the bottom chip in the stack when the current densities were crossing 1000A/Cm^2. I think there are going to be challenges in electro/stress-migration in Cu pillars or bumps that interconnect these, requiring a larger number -increased area & cost.