PORTLAND, Ore.—Intel Corp. says it has designed its first processor built from the ground up for the "green" datacenters of the future, claiming a 70 percent increase in performance for the same energy consumption. The new E5-2600 also features a high-speed bi-directional ring encircling its up to eight cores per socket connecting up to 20 Mbytes of cache, quad DDR3 memory controllers and 40-lanes of PCI-Express 3 for input/output (I/O).
"The E5 is our first CPU optimized for the energy-efficient datacenter of 2015," said Jeff Gilbert, Sandy Bridge architect. "It features twin 32-byte wide ultra-high-speed rings going in opposite directions to encircle the eight [Sandy Bridge] cores and connect them to cache."
The E5 family is also Intel's first server processor family with integrated input/output (I/O), rather than using a separate chip, thereby reducing latency by 30 percent while doubling the bandwidth with PCIe3. The E5 is also the first Intel server processor to support LAN-on-motherboard (LOM) by virtue of industry's first integrated 10-Gbit per second Ethernet local-area network (LAN).
Intel also claims the E5 is its first processor optimized for a lowest idle power of 10-20 percent utilization. A sophisticated power management agent puts separate power limits on the whole device, its cores, memory and I/O, then smartly manages them for optimal performance, energy efficiency or other datacenter goals. Using dynamic switching, depending on load conditions and turbo requests, the E5 will automatically switch between "performance" and "low-power" modes plus a new "balance" mode that compensates for turbo requests by adjusting the voltage/frequency of other cores.
For instance, if datacenter managers decide to clamp power at a certain overall level, then the balance mode will adjust some cores down in voltage and frequency to compensate for the heavy load on a turbo-mode core. The new turbo 2.0 mode is also smarter on the E5, employing better thermal management algorithms that keep track of how long a core has been held idle building up "turbo credits" that can be used when over-clocking is invoked.
Besides voltage and frequency scaling for each core, the new power management agent also manages energy efficiency in I/O by dynamically reducing its width in response to workload and thermal management goals. Core power can be scaled from 50-to-95 watts, which likewise scales memory latency from 118-to-64 nanoseconds, while a "unicore" technique scales cache and ring frequency to match.
In all, 23 different parameters are adjusted by the E5's running-average-power-limit architecture. As a result of optimizations enabled by Intel's Node- and Datacenter-Manager software, Intel estimates that up to 40 percent more servers can be installed per rack using E5 processors.
Intel's E5-2600 processors will be available with up to eight cores encircled by a high-speed bi-directional ring connecting caches, memory, direct I/O.
The improvement of power consumption in idle mode is impressive. With heavy virtualization, how often is a barebone server idle?
"...a 70 percent increase in performance for the same energy consumption." Does it mean absolute performance improvement when the CPU is fully utilized at the moment?
It wasn't that long ago that people were writing about ARM unseating Intel in the server market. This is a good example of Intel not sitting idle. ARM may make some inroads into the small server market, but I really think that the data center and high performance server markets will be the domain of Intel for a long time to come.
The datacenters of the future are putting more emphasis on energy efficiency than on bare-bones performance, making Intel's latest server processor a smart move for the king-of-microprocessors. The coolest feature--besides the power saving "balance" mode--is the ultra-high-speed ring surrounding the octal cores, which marries performance to efficiency in a manner reminescent of supercomputer architectures.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.