LONDON – Soitec SA, a supplier of silicon-on-insulator (SOI) wafers, has announced that mobile chip joint venture ST-Ericsson NV has selected planar fully depleted SOI (FD-SOI) technology for use with future mobile chips.
The implementation of the NovaThor mobile application processor and modem on FD-SOI wafers supplied by Soitec (Bernin, France) enables as much as 35 percent lower power consumption at maximum performance, Soitec did not state at what process node it was making the comparison or what it was comparing against, although presumably that would be bulk CMOS at the same geometry.
It is thought that NovaThor family has been developed using bulk CMOS at least until 28-nm CMOS. So it appears that Soitec is announcing the use of FD-SOI for devices designed to be implemented in processes below 28-nm.
"Next-generation mobile consumer devices will need to deliver an even better user experience and higher performance without sacrificing battery life," said Louis Tannyeres, chief chip architect, ST-Ericsson (Geneva, Switzerland), in a statement issued by Soitec. "Together with innovations in overall platform system design, advances in process technology are key to delivering next-level performance and higher power efficiency. The results of our work with STMicroelectronics on FD-SOI have demonstrated that this technology is able to deliver these benefits in a cost-effective manner, while allowing us to differentiate our solutions."
"FD provides a low-risk option for semiconductor companies such as ST-Ericsson that are seeking to take advantage of the benefits of a fully depleted transistor architecture while leveraging existing design and manufacturing capabilities," said Paul Boudre, chief operating officer of Soitec, in the same statment. "This announcement represents the industry's first step toward fully depleted planar CMOS technology, years ahead of when alternative processes will be available from foundries. We are positioned to provide the volume of qualified wafer manufacturing required to enable the industry to speed the adoption of planar fully depleted technology into mainstream mobile applications."
"STMicroelectronics and its partners Leti, Soitec and IBM have invested several years of development in FD-SOI technology, and ST has recently demonstrated the strong differentiation of this technology versus conventional bulk CMOS, both for high-performance and low-power features on several IPs at 28-nm and below," said Joel Hartmann, STMicroelectronics assistant general manager of technology R&D. "This combination makes FD-SOI particularly suitable for wireless and tablet applications where it essentially provides the fully depleted transistor benefits of FinFETs on a planar conventional technology, while allowing advanced back bias techniques, which are not available with FinFETs. We are delighted that it could be adopted by ST-Ericsson for their next generation of products."
Arguments about the use of FinFETs and silicon-on-insulator as alternative means to minimize leakage currents in advanced process have run for some years. Intel is expected to introduce FinFETs in its 22-nm process technology, although production of processors on 22-nm has reportedly been pushed back to the middle of 2012.
Foundries and other manufacturers who have tended to work together under the auspices of the IBM-driven Common Platform Alliance are not expected to introduce FinFETS until the introduction of their 14-nm processes at the earliest.
The use of fully-depleted SOI wafers increases the base wafer cost but Soitec argues it allows the implementation of transistor technology that solves scaling, leakage and variability issues associated with shrinking CMOS technology from 28-nm with less complexity, thereby enhancing manufacturability and yield.
As I wrote in May, ST-E reckons that w/FD-SOI's power savings, they can add a full extra day for smartphone users (see http://www.advancedsubstratenews.com/2012/05/novathor-smartphone-chip-on-28nm-fd-soi-st-ericsson-blogger-tells-all-pc-mag-sees-light/), which is huge.
And IBS says that even counting the cost of the wafer, per-die FD-SOI comes in at about *half* the cost of bulk (planar and/or FinFET) at 20nm (which ST has in very-fast-follow), because it saves process steps -- see http://www.advancedsubstratenews.com/2012/11/ibs-study-concludes-fd-soi-most-cost-effective-technology-choice-at-28nm-and-20nm/
I believe that ST-Erikson are willing to pay extra for their wafers in order to reap the 40 percent savings in battery power, which mitigates the risk. The other guys are just validating that they can get the higher performance, and by the time they get to volume production, the price may have gone down due to high demand. Of course, bulk silicon will always be cheaper for the raw wafers.