SAN JOSE, Calif. – Electronics companies need to step up their collaboration to deal with growing complexity of the technology, said executives from Cadence, TSMC and ARM at an annual Cadence user event here.
“Silicon integration and complexity will be a real challenge,” said Lip-Bu Tan, chief executive of Cadence, noting 20 nm chips with eight billion transistors in the works.
Tan cited Apple, Oracle, Google and Facebook as examples of companies engaged in “applications-driven system design,” spanning everything from silicon to software. “This will begin changing the landscape of semiconductor design,” said Tan.
Mobile, video and cloud are driving system design, said Cadence's Tan.
“We have lots of products coming out at the eight-billion transistor level, just two billion transistors is becoming passé,” said Rick Cassidy, president of TSMC North America, “Working earlier together is an imperative to have the solution set in place,” he added.
ARM, Cadence and TSMC provided an example of such collaboration with the announcement of a recent tape out of an ARM Cortex A15 core in a TSMC 20 nm process using Cadence tools.
At 20 nm double patterning with 193 mm lithography becomes a requirement, Cassidy told the crowd of about 600 Cadence users here. At 14 nm, certain critical layers will require triple patterning with 193 mm litho, he said in response to a question from EE Times
after the keynotes.
Beyond that, “there’s a race between extreme ultraviolet and direct write litho techniques” for the future of lithography, he added.
3-D transistors and chip stacks are logical candidates for the next big collaboration between the three companies, suggested Tom Lantzsch, executive vice president of ARM, in his keynote.
“3-D transistors have all new challenges in design and it’s critical for us” to master them, Lantzsch said. With the 20 nm A15 tape out, “we have never been involved earlier, and we need to do more of this,” he added.
As for 3-D chip stacks, they “really change the way you should be thinking about how you architect new products,” said TSMC’s Cassidy in his keynote. “There’s a great deal system designers can do to solve problems in different ways then they have ever done before,” he said, noting TSMC now has 3-D IC solutions as part of its 12.0 reference flow.
Cassidy also referred to a MugFET as part of his talk, but didn’t clarify whether it was a 3-D transistor. For its part, Cadence has announced silicon blocks for Wide I/O memory, a key component for 3-D stacks expected in mobile applications processors. It has not yet released an EDA tool for 3-D stacking, a spokesman said.
All sides agreed the long term outlook for the semiconductor business is strong.
“Clearly Q1 is a little but soft, but all execs I talk to say Q2 is looking stronger,” said Tan, noting one industry index is up over 50 percent for the first time since late 2010.
“Semiconductors are at heart of all devices. I convinced my two sons to focus on semiconductors and become EEs--I am so proud of them--it’s a golden opportunity going forward,” Tan said.
14 nm processes will require some triple-patterning, said Cassidy of TSMC.