Breaking News
News & Analysis

TSMC, Altera team on 3-D IC test vehicle

3/22/2012 05:00 PM EDT
1 Comment
More Related Links
View Comments: Newest First | Oldest First | Threaded View
User Rank
re: TSMC, Altera team on 3-D IC test vehicle
docdivakar   3/22/2012 7:42:18 PM
Hi Dylan, this appears to be a process improvement of the more general die-to-wafer bonding which is being used by many in 3D IC stacking. Seems like some details are missing here... how does TSMC handle the assembled and subsequently thinned to minimize manufacturing-induced warping? MP Divakar

August Cartoon Caption Winner!
August Cartoon Caption Winner!
"All the King's horses and all the KIng's men gave up on Humpty, so they handed the problem off to Engineering."
Top Comments of the Week
Like Us on Facebook Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Flash Poll
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.