SAN FRANCISCO—Claiming an industry first, foundry Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and programmable logic vendor Altera Corp. Thursday (March 22) announced the joint development of a heterogeneous 3-D IC test vehicle using TSMC's chip-on-wafer-on-substrate integration process.
TSMC (Hsinchu, Taiwan) said its chip-on-wafer-on-substrate process is an integrated process technology that attaches device silicon chips to a wafer through a chip-on-wafer bonding process. The chip is attached to the substrate to form the final component. By attaching the device silicon to the original thick wafer silicon before it finishes the fabrication process, manufacturing-induced warping is avoided, TSMC said.
TSMC said it plans to offer the chip-on-wafer-on-substrate process as a turnkey manufacturing service. Companies developing 3-D ICs can utilize it as an end-to-end solution that includes the front-end manufacturing process as well as back-end assembly and test solutions, the company said.
Altera (San Jose, Calif.), a longtime TSMC customer, is the first semiconductor company to develop and complete characterization of a heterogeneous test vehicle using TSMC's chip-on-wafer-on-substrate process, the companies said. This and additional test vehicles will enable Altera to quickly test the capabilities and reliability of 3-D ICs to ensure they meet yield and performance targets, the company said.
Bill Hata, senior vice president of worldwide operations and engineering at Altera, said in a statement that the company's partnerships with standards bodies like IMEC and SEMATECH and its use of TSMC's chip-on-wafer-on-substrate process put the firm in good position to deliver heterogeneous 3-D devices to its customers at the right time and with the right set of features. "Implementing heterogeneous 3-D capabilities into our devices enables us to continue our path of technology innovation and leadership, and carry us beyond Moore's Law," Hata said.
Hi Dylan, this appears to be a process improvement of the more general die-to-wafer bonding which is being used by many in 3D IC stacking. Seems like some details are missing here... how does TSMC handle the assembled and subsequently thinned to minimize manufacturing-induced warping?
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