SAN JOSE, Calif. – At next week’s Design West conference, Micron will discuss the road map for its Hybrid Memory Cube, one of the high profile initiatives in a growing wave of 3-D chip stacks. The memory maker is adding new supporters and specifications around its plan for a release of an ultra-dense memory device in the first half of next year.
Micron hopes to name two new supporters in the next few weeks to its currently slate of six companies. It already has backing from Altera, OpenSilicon, Samsung, Xilinx and IBM which made a prototype cube in a 32 nm process. Last September, Intel showed a research project on a physical-layer device that worked with Micron’s cube.
The Hybrid Memory Cube is a stack of four to eight DRAM die linked in a 3-D IC chip stack using through silicon via. They are joined to a logic die that can handle both the RAS/CAS memory-array access jobs of a DRAM chip and the system memory controller functions typically done by a separate chip.
Designers envision placing the Micron stack on a chip substrate next to a server or network processor to provide new levels of fast memory access for high performance systems. Micron says it will deliver early next year 2 and 4 Gbyte versions of the stack providing aggregate bi-directional bandwidth of up to 160 Gbytes/second.
Members of Micron’s consortium are still debating exactly what jobs the logic layer in the stack should support, particularly as the latest server processors already embed memory controllers. Micron prefers to provide the full complement of DRAM and system control in the cube.
The debate is one of the central issues in creating an interface for the cube. Micron and partners hope to deliver a draft of that interface in June, initially open only to members of its consortium of partners. Another issue is whether or how to support atomic transactions, a method for aggregating tasks particularly helpful for multicore processors.
The cube spec in development is described as a high-speed serial interface using a packet protocol. Micron hopes the group can finish the spec by the end of the year, making it generally available on a royalty-free basis.
Micron is not alone in the pursuit of a 3-D memory stack. The Jedec group is working on a follow on to the 12.8 Gbit/second Wide I/O interface that targets mobile applications processors. The so-called HB-DRAM or HBM effort is said to target a 120-128 Gbyte/second interface and is led by the Jedec JC-42 committee including representatives from Hynix and other companies.
@sharps_eng: yes, you are right about the thermal challenges in the stack and this will have some limitations on the logic die. The hybrid memory cube site claims the memory cube will consume 70% less energy per bit than DDR3 DRAM memories but will deliver 15x the performance. This remains to be seen.
Aren't these things going to get pretty hot with certain patterns of usage and data?
For instance if the access pattern does not allow the stacked devices time to cool off between bursts? The internal layers are short on cooling opportunities that's for sure.
Perhaps they can rely on certain friendly usage patterns, with particular cache controllers and DMA engines in specific architectures etc.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.