SAN JOSE, Calif. – Texas Instruments will take its Keystone architecture into low power applications with three new family members introduced at Design West. The single and dual-core DSPs consume from 2 to 3.5W.
The TMS320C6657 features two 1.25 GHz DSP cores, delivering up to 80 GMACs and 40 GFLOPs. The C6655 and C6654 are single-core parts providing up to 40 GMACs and 20 GLOPS and 27.2 GMACs and 13.6 GLOPS, respectively.
The three chips are pin-compatible and sell for prices starting at $30 in ten thousand unit quantities. They are aimed at a wide range of applications including industrial automation, testers, embedded vision, imaging, video surveillance, medical, audio and video infrastructure
“The real goal of these devices is to meet small footprint and small power consumption requirements for portable and small form factor embedded devices that get close to a sensing point,” said Tom Flanagan, director of technical strategy in Texas Instruments’ wireless infrastructure group.
Separately in a keynote at the Multicore Expo at Design West, a TI executive will make the case that multicore heterogeneous SoCs with a mix of DSPs and hardware accelerators can outperform parallel graphics processors and multicore server CPUs.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.