PORTLAND, Ore.—The possible pathways down to the 8-nanometer semiconductor fabrication node were detailed last week at the ACM International Symposium on Physical Design (ISPD) in Napa, Calif., albeit through a glass darkly. What's for sure is that the pathway is fraught with engineering peril as three competing technologies tool up for mass production capabilities. However, keynote speaker Burn Lin, a TSMC distinguished Fellow, claimed that one of three alternatives was sure to surmount the downward scaling hurdles to 8-nm design rules.
The three alternative pathways were 193-nanometer immersion lithography supplemented with multi-patterning, extreme ultraviolet (EUV) lithography and e-beam lithography. Immersion is closest to realization, according to Lin, but only if it can surmount spiraling cost barriers. EUV at the 13.5-nanometer wavelength has already been demonstrated capable of sub-20-nanometer design rules, but needs better focusing mechanisms and higher output light sources to overcome reflectivity of optics as low as 65 percent. E-beam is known to be able to achieve the 8-nanometer node today, but is a last-resort technology due to its slow speed and low throughput.
To solve e-beam's throughput problems, Lin described efforts to use massively parallel e-beams at KLA-Tencor Corp. (Milpitas, Calif.) and Mapper Lithography BV (Delft, the Netherlands), allowing thousands of simultaneous beams to speed throughput, albeit only if reliability, uniformity and accuracy can be improved.
One of the best paper nominees at this year's ISPD was from professor Yao-Wen Chang’s group at National Taiwan University, which addressed the overheating problems of massive e-beam writing processes, achieved by reordering the writing sequence to better control dimensional distortions.
One of the invited talks at ISPD was given by research scientist Kanak Agarwal at IBM Research (Austin, Texas) who described how shape tolerance on layout polygons could help advanced node lithography. He also described two manufacturing methods for harnessing these polygons using mask- and layout-optimization.
Mapper Lithography (Delft, the Netherlands) uses more than 10 thousand beamlets operating simultaneously as it aims for migration down to the 8-nanometer node.
Using a hybrid 3-D integration technique, Cheng's memory structure sandwiched the memristive material between the perpendicular lines of a crossbar at the astronomical density of 100,000 gigabits-per-square-centimeter with 1 billion gigabits-per-second bandwidth.
The biggest challenge of the design was to overcome the mismatch between the fine-grain dimension of the crossbar-based devices and the interface pins of the chip, which Cheng overcame with novel 3-D vias that were tilted with respect to the interface pins.
The best paper award was given to Professor Chirs Chu at Iowa State University, who proposed an algorithm for determining the optimal circuit block shape in VLSI fixed-outline floor-planning, achieving a 10-to-100 increase over previous state-of-the-art techniques.
ISPD also honored Professor Dave C.L. Liu at the National Tsing Hua University (Hsinchu, Taiwan), who also recently received the Phil Kaufman Award for his pioneering work in the physical design of VLSI circuits.
There was a lot more going on at ISPD that I could not include in the story, but you might want to check out on their webiste:
Here are a few highlights: Three talks were given professor Liu’s former students--Jason Cong, a chancellor’s professor and director of the Center for Customizable Domain-Specific Computing of UCLA, spoke on how Liu "Transformed Ad Hoc EDA to Algorithmic EDA." Professor Martin D. F. Wong at University of Illinois (Urbana-Champaign) spoke on how Liu applied simulated annealing to re-shape the EDA landscape. And Synopsys Fellow Tong Gao and his colleague Prashant Saxena spoke on Liu's visionary intuition in the identification and formulation of several issues in routing, interconnect crosstalk optimization and performance-aware layer assignment that subseaquently had wide influence over the semiconductor and EDA industries.
There was also the annual contest, this year on discrete gate sizing, organized by an Intel team led by research scientist Mustafa Ozdal at Intel Strategic CAD Labs. 32 academic and industrial teams from four different continents entered the contest with 18 teams making it through to the submissions phase. The winner was team from National Taiwan University led by professpr Yao-Wen Chang and his graduate students Kuan-Hsien Ho, Po-Ya Hsu, and Yu-Chen Chen. Second plance went to a team from Universidade Federal do Rio Grande do Sul, Brazil, led by professor Marcelo Johann. And third place went to a joint team of National Tsing-Hua University and Missouri University of Science and Technology led by professors Yiyu Shi and Shih-Chieh Chang.
I think there is a hidden extra cost coming down the line just from the fact that three different solutions are being tooled in parallel since no one knows which will make it. All of these approaches are expensive by themselves. Having to hedge your bets by tooling all three is very costly and the foundries will have to recoupe that cost some how.