SAN FRANCISCO—Intel Capital, the venture capital arm of Intel Corp., and programmable logic vendor Xilinx Inc. provided an unspecified amount of funding to EDA startup Oasys Design Systems Inc., Oasys said Tuesday (April 10).
Oasys (Santa Clara, Calif.), which provides physical synthesis tools for designing and implementing ICs with more than 20 million gates, said it would use the Series B funding to expand its research and development team and further expand its worldwide support structure.
“Oasys' technology has the potential to positively impact the design flow for VLSI chip implementation," said Shishpal Rawat, director of business enabling programs for Intel's Design Technology Solutions Group, in a statement. "This is a new way of thinking for next-generation chip design implementation."
Oasys claims its RealTime Designer is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs and produces better results in a fraction of the time needed by traditional logic synthesis products. RealTime Designer features a unique RTL placement approach that eliminates unending design closure iterations between synthesis and layout, according to the company.
Oasys has announced several customers among U.S. semiconductor companies, including Texas Instruments Inc., Qualcomm Inc. and Xilinx.
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