SANTA CLARA, Calif. – A top Nvidia engineer is calling for a move to 450mm wafers as one part of the solution to the growing complexity, cost and time-to-market challenges in chip design.
A diverse host of new technologies and methods will be needed to keep the industry on track to profitably deliver a trillion-transistor device by the end of the decade, said Sameer Halepete, vice president of VLSI engineering at Nvidia. “The challenges are similar to what they were before, and though their nature has changed, I’m very confident we will surmount them,” Halepete said in a keynote at a Mentor Graphics user conference here.
The industry needs to move to 450mm wafers to deal with the increasing number of masks and process steps required to make chips, he told EE Times in a discussion before the keynote. The larger wafers would spread the costs out among more chips and reduce the processing time per chip, he said.
However, Halapete said he is not seeing any signs the shift to the larger wafers will come in time for the 14nm process node. That’s the next big jump after the 28nm chips Nvidia and others are just starting to deliver.
Indeed, it will be difficult to “make the economics work out,” for 450mm wafers, said Wally Rhines, chief executive of Mentor in a talk with EE Times after his keynote here. Five companies including Intel, Samsung and TSMC now account two-thirds all purchases of the chip-making equipment, and they are the ones who need the larger wafers most, he said.
“These companies will have to make the shift happen because many [smaller] companies won’t be able to take advantage of [the larger wafers] for a long time,” Rhines said. The top chip makers “are powerful enough” to drive the shift “but they need to make investments in a judicious way,” he said.
Nvidia’s call for 450mm wafers comes as it and many other fabless companies are dealing with a shift in the business model of TSMC. The Taiwan foundry giant started charging customers for each wafer rather than for each working chip with the 40nm generation, a business model TSMC is said to now use broadly.
The move means fabless companies must assume more of the risk of low yields. Other foundries are expected to adopt the TSMC model eventually, Halepete said.
While what you say is right, it has nothing to do with the topic.
Just because one can create and manufacture a design with more transistors does not mean that the die will work.
If there are twice the logic transistors per chip then the reliability of every one must "double" too.
So Nvidia has found the Design-Gap that has been making the news the past decade. I wonder if they have considered to train more of the required engineers? Or are they saying that they can not turn 1000 Bachelors into physical design engineers? Where did they suppose to find increasing numbers of experienced physical design engineers?
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